DETAILED ACTION
Notice to Applicant
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
2. Claims 1-11 are pending.
Priority
3. Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 112
4. The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
5. Claim 11 is rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Per claim 11, the limitations “the failure detection circuit” in line 1 and “the target circuit” in line 2 lack sufficient antecedent bases. Appropriate correction is required. For the purpose of examination, said limitations are interpreted as implying “a failure detection circuit” and “a target circuit,” respectively.
Claim Rejections - 35 USC § 102
6. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
7. Claims 1-2 and 10-11 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Rohleder et al. (US 2011/0317802 – hereinafter “Rohleder”).
Per claim 1, Rohleder teaches a fault detection circuit (Fig. 5; circuit 504; ¶25) provided in a target circuit (Fig. 7; synchronous circuit 708; ¶28) having a first circuit area that operates in synchronization with a first clock signal (Fig. 5; clock signal 500; ¶25) comprising:
a first detection circuit (Fig. 5; combination of rising-edge counter 512 and rising-edge incrementer 528; ¶25) for outputting a first detection result obtained by transitioning a voltage level in synchronization with the first clock signal (A rising-edge counter 512 is triggered by the rising edges in a clock signal 500 and outputs a rising-edge count (Fig. 5; ¶25)),
a second detection circuit (Fig. 5; combination of falling-edge counter 542 and falling-edge incrementer 558; ¶25) for outputting a second detection result obtained level by transitioning the voltage in synchronization with the first clock signal (A falling-edge counter 542 is triggered by the falling edges in the clock signal 500 and outputs a falling-edge count (Fig. 5; ¶25)), and
a first comparison circuit (Fig. 5; comparator 574; ¶25) for outputting a first comparison result by comparing the first detection result and the second detection result (The comparator 574 is configured to output a comparison result by comparing the rising-edge count and the falling-edge count (Fig. 5; ¶25)).
Per claim 2, Rohleder teaches a failure detection circuit according to claim 1, when the first detection result and the second detection result match, the first comparison circuit outputs the first comparison result indicating that a failure has not occurred in the first circuit area, when the first detection result and the second detection result do not match, the first comparison circuit outputs the first comparison result indicating that a failure has occurred in the first circuit area (When the rising-edge count and the falling-edge count match, an error signal is not generated. When the rising-edge count and the falling-edge count differ, an error signal may be generated indicating that a clock glitch has been detected (Fig. 5; ¶25)).
Per claim 10, Rohleder teaches a semiconductor device is configured the failure detection circuit and the target circuit according to claim 1 (The elements of system 708 are circuitry located on a single integrated circuit (¶36)).
Per claim 11, Rohleder teaches a failure detection method by the failure detection circuit (Fig. 5; circuit 504; ¶25) provided in the target circuit (Fig. 7; synchronous circuit 708; ¶28) having a first circuit area that operates in synchronization with a first clock signal (Fig. 5; clock signal 500; ¶25),
by using a first detection circuit (Fig. 5; combination of rising-edge counter 512 and rising-edge incrementer 528; ¶25), outputs a first detection result obtained by transitioning a voltage level in synchronization with the first clock signal (A rising-edge counter 512 is triggered by the rising edges in a clock signal 500 and outputs a rising-edge count (Fig. 5; ¶25)),
by using a second detection circuit (Fig. 5; combination of falling-edge counter 542 and falling-edge incrementer 558; ¶25), outputs a second detection result obtained by transitioning the voltage level in synchronization with the first clock signal (A falling-edge counter 542 is triggered by the falling edges in the clock signal 500 and outputs a falling-edge count (Fig. 5; ¶25)),
by using a first comparison circuit (Fig. 5; comparator 574; ¶25), outputs a first comparison result by comparing the first detection result and the second detection result (The comparator 574 is configured to output a comparison result by comparing the rising-edge count and the falling-edge count (Fig. 5; ¶25)).
Claim Objections
8. Claim 10 is objected to due to the following informality.
Per claim 10, it appears that the phrase “is configured” should revised to “comprising” to indicate that the failure detection circuit and the target circuit according to claim 1 are components of a semiconductor device.
9. Claims 3-9 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Per claim 3, the prior art of record is silent on the failure detection circuit according to claim 1, wherein, in particular, “the first comparison circuit compares the first detection result with the second detection result, further compares the third detection result with the fourth detection result, and outputs the first comparison result.” Claims 4 and 6 are consequently objected to due to their dependence on claim 3.
Per claim 5, the prior art of record is silent on the failure detection circuit according to claim 1, further comprising, in particular: the first selector, the first flip-flop, the first inverter, the second selector, the second flip-flop, and the second inverter as described in this claim.
Per claim 7, the prior art of record is silent on the failure detection circuit according to claim 1, wherein the target circuit further includes the third detection circuit, the fourth detection circuit, and the second comparison circuit as described in this claim. Claims 8-9 are consequently objected to due to their dependence on claim 7.
Conclusion
10. Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAS A. SANGHERA whose telephone number is (571)272-4787. The examiner can normally be reached M-Th, alt. Fri, 8-5 EST.
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/JAS A SANGHERA/Primary Examiner, Art Unit 2852