Prosecution Insights
Last updated: August 15, 2026
Application No. 18/773,993

LOAD DRIVE CIRCUIT CAPABLE OF STOPPING OPERATING UPON OCCURRENCE OF ABNORMALITY, AND METHOD OF CONTROLLING LOAD DRIVE CIRCUIT

Non-Final OA §102
Filed
Jul 16, 2024
Priority
Jul 28, 2023 — JP 2023-123067
Examiner
POOS, JOHN W
Art Unit
Tech Center
Assignee
Minebea Mitsumi Inc.
OA Round
1 (Non-Final)
94%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
98%
With Interview

Examiner Intelligence

Grants 94% — above average
94%
Career Allowance Rate
1306 granted / 1397 resolved
+33.5% vs TC avg
Minimal +5% lift
Without
With
+4.6%
Interview Lift
resolved cases with interview
Fast prosecutor
1y 10m
Avg Prosecution
30 currently pending
Career history
1414
Total Applications
across all art units

Statute-Specific Performance

§101
0.9%
-39.1% vs TC avg
§103
30.2%
-9.8% vs TC avg
§102
55.1%
+15.1% vs TC avg
§112
5.1%
-34.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1397 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1 and 4 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Neunaber (US 2004/0178852). In regard to Claim 1: Neunaber discloses, in Figure 3, a load drive circuit capable of stopping operating upon occurrence of an abnormality, the load drive circuit comprising: a drive circuit (40) configured to receive a power source voltage from a power source circuit (62), to drive a load (46) while the drive circuit (40) is receiving an enable signal (60) at an enable level, and to stop driving the load (46) while the drive circuit (40) is receiving the enable signal (60) at a disable level (¶ 0066), the power source circuit (62) being configured to reduce the power source voltage in response to a power source current exceeding a limit value (¶ 0068); a voltage reduction detection circuit (68) configured to output a first detection signal at an enable level when the power source voltage is lower than a first voltage, and to output the first detection signal at a disable level when the power source voltage is equal to or higher than the first voltage (¶ 0042-0043); and an enable control circuit (58) configured to output the enable signal (60) at the disable level based on the first detection signal being at the enable level (¶ 0045), and to output the enable signal (60) at the enable level based on the first detection signal being at the disable level (¶ 0059). In regard to Claim 4: Neunaber discloses, in Figure 3, a method of controlling a load drive circuit configured to drive a load (46) by receiving a power source voltage from a power source circuit (62) configured to reduce the power source voltage in response to a power source current exceeding a limit value (¶ 0032), the method comprising: driving (40) the load (46) while an enable signal (60) at an enable level is being received (¶ 0066), and stopping (40) driving the load (46) while the enable signal (60) at a disable level is being received (¶ 0068); outputting a first detection signal (48 output) at an enable level when the power source voltage is lower than a first voltage, and to output the first detection signal (48 output) at a disable level when the power source voltage is equal to or higher than the first voltage (¶ 0042-0043); and outputting the enable signal (60) at the disable level based on the first detection signal being at the enable level (¶ 0045), and outputting the enable signal (60) at the enable level based on the first detection signal being at the disable level (¶ 0059). Allowable Subject Matter Claims 2-3 and 5 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. In regard to Claim 2: None of the prior art or combination thereof teaches or fairly suggests the following features in combination with the other limitations of the claims: the load drive circuit further comprising: a temperature detection circuit configured to output a second detection signal at an enable level when a temperature is equal to or higher than a first temperature, and to output the second detection signal at a disable level when the temperature is lower than the first temperature, wherein the enable control circuit outputs the enable signal at the disable level based on the first detection signal being at the enable level or the second detection signal being at the enable level, and outputs the enable signal at the enable level based on the first detection signal being at the disable level and the second detection signal being at the disable level. In regard to Claim 5: None of the prior art or combination thereof teaches or fairly suggests the following features in combination with the other limitations of the claims: wherein the drive circuit is an audio amplifier comprising: a first amplifier configured to receive at a pair of first input terminals thereof, an input signal that is input via a filter, and a standard voltage, respectively, and to output a first output signal via a first output terminal; and a second amplifier configured to receive at a pair of second input terminals thereof, the standard voltage and a third voltage, respectively, and to output a second output signal via a second output terminal, the third voltage is a voltage that is output from between resistors that are connected in series between the first output terminal and the second output terminal, However, Neunaber discloses, in Figure 3, the load is a loudspeaker (46) configured to receive the first output signal (44) at a first input terminal thereof, and to receive the second output signal (ground) at a second input terminal thereof (¶ 0039). Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Yamamoto et al. (US 2006/0093153) discloses a power supply voltage detection circuit detecting whether voltage applied to a power supply terminal is used for a dynamic speaker or a piezoelectric speaker. Kitamura (US 2004/0028242) discloses a control loop for sensing the fluctuation of the source voltage (V.sub.0) of a power amplifier (3) to feed it back to a switching regulator (5) is provided as well as a control loop to feed it forward to the switching regulator (5) by using PWM signal serving as the source for drive control of the power amplifier (3). Arai et al. (US 2018/0196457) discloses A regenerative current detection circuit includes a first power MOS transistor that is configured as a current mirror to a second power MOS transistor connected to drive a motor winding, a first feedback amplifier that compares a first regenerative current that flows in the first power MOS transistor with a second regenerative current that flows in the second power MOS transistor and outputs a comparison result. Any inquiry concerning this communication or earlier communications from the examiner should be directed to John W Poos whose telephone number is (571)270-5077. The examiner can normally be reached M-Th 8-5. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Han can be reached at 571-272-2078. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JOHN W POOS/Primary Examiner, Art Unit 2843
Read full office action

Prosecution Timeline

Jul 16, 2024
Application Filed
Jul 16, 2026
Non-Final Rejection mailed — §102 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
94%
Grant Probability
98%
With Interview (+4.6%)
1y 10m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1397 resolved cases by this examiner. Grant probability derived from career allowance rate.

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