Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
FINAL REJECTION
This Office Action addresses U.S. Patent Application No. 18/774,324 entitled “SENSE AMPLIFIER CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME”, filed July 16, 2024, and claims priority from Korean Patent Application KR20250090548A, filed December 13, 2023.
Claims 1-20 are pending.
DRAWING OBJECTIONS
The drawings filed February 27, 2026 are objected to under 37 CFR 1.83(a) because:
(1) The drawings are not in accordance with 37 CFR 1.84(l), which states, “Every line, number, and letter must be durable, clean, black (except for color drawings), sufficiently dense and dark, and uniformly thick and well-defined.”
The drawings are not uniformly dark as were the originally filed drawings. It appears that some resolution was lost in reproduction. For example:
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(2) Replacement Sheets were submitted along with original copies of the drawings, such that all were entered, causing duplicate drawing views.
A corrected submission with clear reproductions and only Replacement Sheets is required. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
SPECIFICATION
The previous objections to the title of the invention, the abstract and the summary of the invention are withdrawn due to the amendments filed February 27, 2026.
The disclosure is objected to because of the following informalities:
The reference characters “100 a”, “110 b”, “110 a” and “110 b” should be amended in the specification to “100a”, “110b”, “110a” and “110b”, respectively, in accordance with the drawing figures.
Note: This rejection is maintained from the previous Office action, but would be overcome with the filing of corrected copies of the proposed drawings filed February 27, 2026.
Appropriate correction is required.
CLAIM INTERPRETATION
The amended claims have been reviewed in an updated analysis under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. To invoke 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, a claimed phrase must meet the three prong analysis as set forth in MPEP § 2181, subsection I.
The amended claims do not invoke 35 U.S.C. § 112, 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. § 112, sixth paragraph.
CLAIM REJECTIONS - 35 USC § 112, 1st PARAGRAPH
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the enablement requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to enable one skilled in the art to which it pertains, or with which it is most nearly connected, to make and/or use the invention.
Claims 1, 18 and 20 now recite “directly connected to the precharge voltage”. However, this language is not in the specification. There is occurrence of “directly connected” in the specification, including with regard to the precharge voltage.
The specification in ¶ [0034] states, “The plurality of bitline sense amplifiers BLSA may receive a precharge voltage VBL. For example, the precharge voltage VBL may be provided to the equalizer circuit. For example, as will be described with reference to FIGS. 3 and 7, the equalizer circuit may include an equalizing transistor, and the precharge voltage VBL may be applied to a source (or a source electrode or a first electrode) of the equalizing transistor.”
Thus, while the precharge voltage may be applied to the source, there is no limitation that the voltage be “directly connected” to the source.
Claims 2-17 and 19 are rejected as being dependent on their respective base claims.
CLAIM REJECTIONS - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-4, 11, 12, and 18-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yang et al., U.S. Patent Application Publication No. 2023/0230630.
Yang et al. (hereinafter, “Yang”) is directed to a readout circuit architecture 10 includes a sense amplifier 20. The sense amplifier 20 includes a readout amplification unit 101 and a first offset compensation unit 102. The readout amplification unit 101 is configured to amplify a target voltage on a readout bit line SABLT and a complementary readout bit line SABLB. The readout amplification unit 101 includes a first P-type transistor and a second P-type transistor. The first offset compensation unit 102 is configured to connect a control terminal of the first P-type transistor and a control terminal of the second P-type transistor to a preset voltage VBIAS in response to an offset cancelling OC signal. The first offset compensation unit 102 includes a first offset compensation transistor and a second offset compensation transistor.
Note Yang, Figure 1 below:
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Note also the following comparison of Yang, Figure 11 with Figure 11 of the present invention:
Yang 18/774,324
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Yang teaches independent claim 1 as follows:
a sense amplifier circuit (note, e.g., Figure 10) comprising:
a plurality of bitline sense amplifiers (e.g., sense amplifiers 20),
wherein each of the plurality of bitline sense amplifiers includes:
an amplifying circuit electrically connected to a bitline (Figure 1, BLT) and a complementary bitline (Figure 1, BLB), the amplifying circuit configured to sense a voltage difference between the bitline and the complementary bitline and to adjust a voltage (¶ [0012], “The readout amplification circuit is configured to amplify a target voltage on a readout bit line and a complementary readout bit line”) of a sensing bitline (Figure 1, readout bitline, SABLT) and a complementary sensing bitline (Figure 1, complementary readout bitline, SABLB) based on the voltage difference (note e.g., ¶ [0155], “A device difference between the first P-type transistor 201 and the second P-type transistor 202 results in a voltage difference between the complementary readout bit line SABLB and the readout bit line SABLT, and then a threshold voltage difference between the first P-type transistor 201 and the second P-type transistor 202 is compensated through the voltage difference between the complementary readout bit line SABLB and the readout bit line SABLT”);
an isolation circuit configured to electrically connect the bitline and the complementary bitline with the complementary sensing bitline and the sensing bitline, respectively (¶ [0013], “The isolation circuit is configured to connect a bit line to the complementary readout bit line and connect a complementary bit line to the readout bit line in response to an isolation signal, and connect a control terminal of the P-type transistor to the readout bit line or the complementary readout bit line”);
an offset cancellation circuit configured to electrically connect the bitline and the complementary bitline to the sensing bitline and the complementary sensing bitline, respectively (¶ [0015], “The second offset compensation circuit is configured to connect the bit line to the readout bit line and connect the complementary bit line to the complementary readout bit line in response to the offset cancelling signal”); and
an equalizer circuit configured to equalize the bitline and the complementary bitline to a precharge voltage (¶ ¶ [0148]-[0150], “The sense amplification circuit 30 is configured to read out and write back the data stored in the memory cell 40, which includes the following processes in combination with FIG. 10 , FIG. 11 and FIG. 12 .
S1, a pre-charging stage.The first isolation signal ISOP, the second isolation signal ISON, the offset cancelling OC signal and the equalizing signal EQ are provided”),
wherein the equalizer circuit includes an equalizing transistor (¶ [0045], “The equalizing unit 105 includes an equalizing transistor” and equalizing transistor 213) that has a source directly connected to the precharge voltage (¶ [0147], “The first isolation signal ISOP, the second isolation signal ISON, the offset cancelling OC signal and the equalizing signal EQ are provided, and the first offset compensation transistor 203, the second offset compensation transistor 204, the first isolation transistor 207, the second isolation transistor 208, the third isolation transistor 209, the fourth isolation transistor 210, the third offset compensation transistor 211, the fourth offset compensation transistor 212 and the equalizing transistor 213 are all in a turn-on state/a conducting state, so that the bit line BLT, the readout bit line SABLT, the complementary bit line BLB and the complementary readout bit line SABLB are pre-charged to the preset voltage VBAIS”). Figure 10 shows how VBIAS is connected through the offset compensation transistor to the isolation transistor to the equalizing transistor 213. Since these are all pre-charged to VBIAS in a conducting state, the pre-charge voltage VBIAS is being directly fed into the source of transistor 213, because that is the prevailing voltage on the lines at the time of pre-charge), a gate configured to receive an equalizing signal, and a drain (note Figure 10), and
wherein an active region (i.e., active area) is formed such that sources of equalizing transistors of a first bitline sense amplifier and a second bitline sense amplifier are connected to each other (¶ [0052], “the third active areas A3, where the sources or drains of the first offset compensation transistors 203 of the multiple groups of sense amplifiers 20 are located, are interconnected; and the fourth active areas A4, where the sources or drains of the second offset compensation transistors 204 of the multiple groups of sense amplifiers 20 are located, are interconnected” and see below) and sources of equalizing transistors of the first bitline sense amplifier and a third bitline sense amplifier are separated from each other (¶ [0133], “the active areas where the other terminals are located are not interconnected” and see below).
Yang teaches the invention as described above, but explains that the offset compensation transistors are interconnected and/or separated (as opposed to the claimed equalizing transistors being connected or separated), however it is noted that both achieve the same result, a compensation and equalization of the voltages. Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was made that sources of equalizing transistors of a first bitline sense amplifier and a second bitline sense amplifier are connected and that sources of equalizing transistors of a first bitline sense amplifier and a third bitline sense amplifier are not connected, since (1) Yang taught that “the first offset compensation transistor 203 and the second offset compensation transistor 204 are located are interconnected, and the active areas where the other terminals are located are not interconnected” (¶ [0133]), (2) Yang taught similar connections with the equalizing transistors “A control terminal of the equalizing transistor 213 is configured to receive the equalizing signal EQ, a first terminal of the equalizing transistor 213 is connected to the readout bit line SABLT, and a second terminal of the equalizing transistor 213 is connected to the complementary readout bit line SABLB” (¶ [0147]) and (3) in particular design of the Yang system, this would have been the most efficient way to equalize the voltages.
With regard to claims 11 and 12, note the discussion above with regard to precharging of the of the equalizing transistor 213.
Regarding independent claim 18, the limitations are taught as shown above for claim 1, further including “a memory cell array including a plurality of memory cells” (¶ [0002], “A Dynamic Random Access Memory (DRAM) is a common semiconductor memory device in the computers and is composed of many memory cells” and (¶ [0033]).
Regarding claim 19, note “the semiconductor memory device 200 may be one of various volatile memory devices such as a dynamic random access memory (DRAM)” (¶ [0140]).
Regarding independent claim 20, the limitations are taught as shown above for claim 1, further including “wherein sources of first and second equalizing transistors included in first and second bitline sense amplifiers that are adjacent to each other are connected to each other, and a first active region corresponding to the sources of the first and second equalizing transistors is integrally formed, wherein sources of third and fourth equalizing transistors included in third and fourth bitline sense amplifiers that are adjacent to each other and spaced apart from the first and second bitline sense amplifiers are connected to each other, and a second active region corresponding to the sources of the third and fourth equalizing transistors is integrally formed, and wherein the sources of the first and second equalizing transistors and the sources of the third and fourth equalizing transistors are separated from each other, and an active cut region is formed between the first and second active regions to separate the first active region from the second active region” (note that all of the Yang elements are integrally formed on a semiconductor integrated circuit, note ¶ [0004], with the goal being to “improve the level of integration” ¶ [0037], and regarding the active cut region, note Figure 4, where areas A3 or A4 have sense amplifiers arranged separately).
With regard to claims 2, 3 and 4, note the corresponding citations for claim 20.
RELEVANT PRIOR ART
The examiner notes the following additional references which are also deemed relevant to the present claims. While these references have not been cited in the rejections above, because of their particular relevance, applicant is advised to consider these when formulating any response to this Office action.
(1) Chi, U.S. Patent Application Publication No. 2023/0071414 is directed to “a sense amplification circuit including a PMOS transistor, a source of which is connected to a signal terminal; a NMOS transistor, a source of which is connected to a different signal terminal, where a drain of the PMOS transistor and a drain of the NMOS transistor are connected to a reading bit line, and their gates are connected to a different reading bit line; a second PMOS transistor, a source of which is connected to the first signal terminal; a second NMOS transistor, a source of which is connected to the second signal terminal, where a drain of the second PMOS transistor and a drain of the second NMOS transistor are connected to a first reading complementary bit line, and gates of them are connected to a second reading complementary bit line; a first conduction unit, one terminal of which is connected to the first reading bit line, other terminal of which is connected to an initial bit line; a second conduction unit, one terminal of which is connected to the first reading complementary bit line, other terminal of which is connected to an initial complementary bit line; a first driving unit, configured to turn on the first PMOS transistor or the first NMOS transistor; and a second driving unit, configured to turn on the second PMOS transistor or the second NMOS transistor” (cf. present claim 13).
(2) Kim et al., U.S. Patent No. 10,224,093, is directed to “a sense amplifier which senses a voltage variation of a bit line. The sense amplifier includes a sense amplifying unit connected to the bit line and a complementary bit line, configured to sense a voltage variation of the bit line in response to a first control signal and a second control signal, and configured to adjust voltages of a sensing bit line and a complementary sensing bit line based on the sensed voltage variation, a first isolation unit configured to connect the bit line to the sensing bit line in response to an isolation signal, a second isolation unit configured to connect the complementary bit line to the complementary sensing bit line in response to the isolation signal, a first offset cancellation unit configured to connect the bit line to the complementary sensing bit line in response to an offset cancellation signal, and a second offset cancellation unit configured to connect the complementary bit line to the sensing bit line in response to the offset cancellation signal. The sense amplifying unit includes a first P-type metal-oxide-semiconductor (PMOS) transistor connected between the first control signal and the complementary sensing bit line and having a gate connected to the sensing bit line, a second PMOS transistor connected between the first control signal and the sensing bit line and having a gate connected to the complementary sensing bit line, a first N-type metal-oxide-semiconductor (NMOS) transistor connected between the second control signal and the complementary sensing bit line and having a gate connected to the bit line, and a second NMOS transistor connected between the second control signal and the sensing bit line and having a gate connected to the complementary bit line” (cf. present claim 13).
RESPONSE TO AMENDMENT
The amendment and associated remarks filed February 27, 2026 have been carefully considered by the examiner.
In the case of the specification, most of the objections have been withdrawn herewith. New drawings objections are made in response to the drawings filed February 27, 2026. With regard to the arguments directed to rejections based on prior art, these are moot in view of the modified rejections made in response to the amendment.
ALLOWABLE SUBJECT MATTER
As explained in the rejections above, the newly amended language “directly connected to the precharge voltage” is taught by Yang. However, this feature is described in claim 6 in a manner that is not taught or suggested by Yang, namely, “wherein the precharge voltage is provided to the first active region through the first and second direct contacts and the first and second bitline metal patterns.”
Thus, claim 1 would be allowable if amended to remove the “directly” language and to include the limitations of claim 6 and any intervening claims.
CONCLUSION
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to B. James Peikari at telephone number (571) 272-4185. The examiner can normally be reached M-F 8:30am - 5:30pm, EST.
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/B. James Peikari/
Primary Examiner, Art Unit 3992