Prosecution Insights
Last updated: July 17, 2026
Application No. 18/774,412

CYCLIC REDUNDANCY CHECK COMPARISON FOR ERROR DETECTION

Final Rejection §103
Filed
Jul 16, 2024
Priority
Sep 27, 2023 — provisional 63/585,768
Examiner
CHASE, SHELLY A
Art Unit
2112
Tech Center
2100 — Computer Architecture & Software
Assignee
Micron Technology Inc.
OA Round
2 (Final)
95%
Grant Probability
Favorable
3-4
OA Rounds
1m
Est. Remaining
97%
With Interview

Examiner Intelligence

Grants 95% — above average
95%
Career Allowance Rate
719 granted / 759 resolved
+39.7% vs TC avg
Minimal +2% lift
Without
With
+2.5%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 1m
Avg Prosecution
19 currently pending
Career history
784
Total Applications
across all art units

Statute-Specific Performance

§101
11.8%
-28.2% vs TC avg
§103
53.5%
+13.5% vs TC avg
§102
10.5%
-29.5% vs TC avg
§112
10.1%
-29.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 759 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claims 1 to 20 are presented for examination. The amendment filed 2-11-2026 cancelled claims 2 and 10. Response to Amendment The rejection of claims 1 to 2, 9 and 15 as being obvious over Schaefer is withdrawn. Response to Arguments Applicant’s arguments with respect to claims 1 to 2, 9 and 15 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Claim Rejections - 35 USC § 103 The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action. Claims 2 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Alves et al. (2011/0320914). Claim 2: Alves teaches a method and an apparatus for error correction and detection in a redundant memory system, the method comprising: a memory controller (110) communicating with a memory system over interface busses (106) (see par. 0019). Alves teaches that the interface busses comprises upstream (108) and downstream (106) communication busses (see par. 0020). Alves teaches that in a RAIM (redundant arrays of independent memory) modules, a “mark” refers to is an indication given to an ECC that a particular symbol or set of symbols of read word are suspected to be faulty (see par. 0022). Alves teaches that if an error is caught by a channel CRC, then a temporary mark is placed which will allow the RAIM ECC to correct additional possible errors (see par. 0023). Alves teaches that memory channel failures may require replacement and if the failure is a correctable error (CE) the data is not destroyed and the operation of the memory is not interrupted; however, if the failure is an uncorrectable error (UE) it will cause the memory to be off-line for a repair (see par. 0024). Alves teaches that a first and second failure are said to be coincident and if the repair time is longer, its most likely that a second failure occur coincident with the first (see par. 0025). Alves teaches that before a second failure is identified, exemplary embodiments provide for immediate correction of a channel failure using marking and allowing for additional correction of the second failure (see par. 0025). Alves teaches that once a channel failure is identified, correction of up to two marked additional memory devices and a new single bit error and if the system has one marked memory device together with the marked channel, then an entire new chip error can be corrected (see par. 0025). Alves teaches that in a RAIM fetch path, a CRC checker (510) is utilized to detect a channel error, and to temporarily mark a failing channel (see par. 0031). Alves teaches that the calculated CRC for data retrieved from the memory chips are checked at the memory controller wherein if the check dose not pass, it is then known that a channel failure has occurred (see par. 0016). Alves teaches that if CRC errors were detected by the CRC checker, then a recovery logic (512) performs a retry of stores and/or fetches where errors have been identified and the system has the ability to have soft errors such as failing memory devices and also channel failures or other internal errors without getting uncorrectable errors, which read on “determining a type of the error based at least in part on a comparison of the first CRC value to the second CRC value wherein the type indicates a cause of the error” (see par. 0032). Alves fails to specifically teach the limitation of “receiving a third indication of a second CRC value corresponding to the data based at least in part on receiving the second indication of the error;” however, this teaching is obvious to the teachings of Alves because Alves teaches that the system provides CRC detection and isolation to channel interfaces as well as, when CRC errors are detected on a channel, the bad channel is temporarily marked to help protect against channel errors (see par. 0034) Alves teaches that the technical effects and benefits include the ability to run a memory system in an unimpaired state in the presence of a memory channel failure occurring coincident with up to two additional memory device failures (see par. 0037). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the system of Alves for detecting and correcting memory and cannel failures that is marked to help protect against channel errors with the limitation of: “receiving a third indication of a second CRC value corresponding to the data based at least in part on receiving the second indication of the error” because Alves teaches that a system for detecting and correcting errors in a channel and in a memory includes identifying errors and marking to help protect against channel errors and the marking allows the ECC to better correct against other errors. This modification would have been obvious because a person of ordinary skill in the art would have been motivated to employ a method and an apparatus to detect and correct errors that can improve a memory system availability and serviceability as taught by Alves (see par. 0038). Claim 15, is similar to claim 2 and is also rejected for the same rational applied to claim 2. Allowable Subject Matter Claims 3 to 5, 7 to 8 and 16 to 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claims 6, 9, 11 to 14 and 20 are allowed. The following is a statement of reasons for the indication of allowable subject matter: the prior art made of record teaches a system for detecting and correcting memory errors and channel errors using CRC and ECC as detailed above; however, the prior art made of record, taken alone or in combination fails to teach or fairly suggest or render obvious the combination of elements of the allowed claims. Specifically, the prior art made of record, failed to teach or fairly suggest or render obvious the combination of limitations of: “receiving a second indication of an error associated with the first CRC value; transmitting based at least in part on receiving the second indication of the error, a command to transmit a third indication of the second CRC value and receiving the third indication of a second CRC value corresponding to the data based at least in part on receiving the second indication of the error, wherein the third indication is received based at least in part on the command” (claims 6 and 9). The prior art made of record taken alone or in combination fails to teach or fairly suggest or render obvious the combination of elements with the novel element of: “calculating, based at least in part on the data, a second CRC value: storing a table of a set of error types, and determining an error type associated with the data based at least in part on a comparison of the first CRC value, the second CRC value, and an expected CRC value associated with the data, wherein determining the error type comprises reading an entry of the table corresponding to the error type in accordance with one or more difference between the first CRC value, the second CRC value, the expected CRC value, or a combination thereof” (claim 20). Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Brewer et al. USPAP 2022/0237077) discloses a system, an apparatus and a method related to memory device protection. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHELLY A CHASE whose telephone number is (571)272-3816. The examiner can normally be reached Mon-Thu 8:00-5:30, 2nd Friday 8:00-4:30. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Albert Decady can be reached at 571-272 3819. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Shelly A Chase/Primary Examiner, Art Unit 2112
Read full office action

Prosecution Timeline

Jul 16, 2024
Application Filed
Nov 17, 2025
Non-Final Rejection mailed — §103
Feb 11, 2026
Response Filed
Jun 02, 2026
Final Rejection mailed — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
95%
Grant Probability
97%
With Interview (+2.5%)
2y 1m (~1m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 759 resolved cases by this examiner. Grant probability derived from career allowance rate.

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