DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Election/Restrictions
Claims 2, 4, and 8-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 08 July 2025.
Applicant’s election without traverse of Species III, corresponding to originally filed Claims 1, 3, and 5-7, in the reply filed on 08 July 2025 is acknowledged.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 and 3 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Gao et al. (hereinafter “Gao” CN-114913801A).
(It should be noted that the Gao reference was initially cited by the applicant via the Information Disclosure Statement received 16 July 2024. It should further be noted that the relevant portions of the Gao reference are cited herein with respect to the accompanying English Language Translation of CN-114913801A.)
As pertaining to Claim 1, Gao discloses (see Fig. 15 and Fig. 16 with Fig. 12, Fig. 14, and Fig. 18) a display device, comprising a display panel (100; see “Specific Implementation” at Page 4, Paragraph [06]), wherein
the display panel (100) includes pixel circuits (1) arranged in multiple rows (see Fig. 15);
each pixel circuit (1; see Fig. 16) includes a light-emitting control transistor (M2) and a driving transistor (M0); wherein: the light-emitting control transistor (M2) is used to control a corresponding light-emitting element (2) to enter a light-emitting stage; and the driving transistor (M0) is used to provide a driving current for the corresponding light-emitting element (2; see “Specific Implementation” at Page 4, Paragraph [07] through Page 5, Paragraph [01]);
a driving process (see Fig. 12, Fig. 14, and Fig. 18) of the display panel (100) includes a first stage (see one cycle time of “Scan1” during (t2) of (T1)) and a display stage (T2), wherein the first stage (again, see one cycle time of “Scan1” during (t2) of (T1)) is located at least before or after the display stage (T2; see “Specific Implementation” at Page 5, Paragraph [02]);
in the first stage (again, see one cycle time of “Scan1” during (t2) of (T1)), at least one of light-emitting control transistors (M2) and driving transistors (M0) in each row of pixel circuits (1) is turned off (see “Specific Implementation” at Page 5, Paragraph [06]); and
a duration of the first stage is t (again, see one cycle time of “Scan1” during (t2) of (T1)), and a data refresh frequency (see Fig. 14 at “Scan1”) of the pixel circuits (1) in the display stage (T2) is f (i.e., a cycle frequency of “Scan1” during (T2)), t<=1/f, wherein the 1/f (i.e., a cycle time of “Scan1” during (T2)) is a duration of a refresh frame or display frame (see Fig. 12, Fig. 14, and Fig. 18 and note that one cycle time of “Scan1” during (t2) of (T1) is equal to a cycle time of “Scan1” during (T2); see “Specific Implementation” at Page 11, Paragraph [05]; Page 12, Paragraph [02]-[03]; and Page 12, Paragraph [07] through Page 13, Paragraph [04]).
As pertaining to Claim 3, Gao discloses (see Fig. 15 and Fig. 16 with Fig. 12, Fig. 14, and Fig. 18) that the light-emitting control transistor (M2) and the driving transistor (M0) are electrically connected between a first power line (PVDD) and a first electrode (i.e., an upper electrode) of a corresponding light-emitting element (2; see Fig. 16); and
in the first stage (again, see one cycle time of “Scan1” during (t2) of (T1)), gates of driving transistors (M0) in each row of pixel circuits (1) are written with a first voltage (VPVDD), wherein the first voltage (VPVDD) is larger than or equal to a voltage (VPVDD) of the first power line (see (PVDD)) during the display stage (T2; see “Specific Implementation” at Page 5, Paragraph [02] and Page 6, Paragraph [06]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Gao in view of Sohn et al. (hereinafter “Sohn” US 11,922,866).
As pertaining to Claim 5, Gao discloses (see Fig. 15 and Fig. 16 with Fig. 12, Fig. 14, and Fig. 18) that the pixel circuit (1) further includes a bias transistor (M7; see the transistor controlled by “Scan2”) and a threshold compensation transistor (M6);
a first electrode (i.e., a lower electrode) of the bias transistor (M7) is electrically connected to a bias signal line (DVH), and a second electrode (i.e., an upper electrode) of the bias transistor (M7) is electrically connected to a first electrode (i.e., the upper electrode) of the driving transistor (M0);
a first electrode (i.e., a right electrode) of the threshold compensation transistor (M6) is electrically connected to the second electrode (i.e., a lower electrode) of the driving transistor (M0), and a second electrode (i.e., a left electrode) of the threshold compensation transistor (M6) is electrically connected to a gate electrode of the driving transistor (M0);
in the first stage (see (t2) or any portion of (t2) in (T1)), bias transistors (M7) and the threshold compensation transistors (M6) in each row of pixel circuits (1) are all turned on (see Fig. 14 and Fig. 18);
the display device (100) further includes a display driving chip (200, 300); and
in the first stage (again, see one cycle time of “Scan1” during (t2) of (T1)), the display driving chip (200, 300) provides the bias signal line (DVH; see “Specific Implementation” at Page 11, Paragraph [05]; Page 12, Paragraph [02]-[03]; and Page 12, Paragraph [07] through Page 13, Paragraph [05]).
Gao does not explicitly disclose the voltage value of the bias signal (DVH). That is, Gao does not explicitly disclose that the bias signal line has the first voltage (VPVDD).
However, in the same field of endeavor, Sohn discloses (see Fig. 1 and Fig. 2) a display device (100; see Col. 7, Ln. 17-24) implementing a pixel circuit (PXL) having a similar structural configuration to that of Gao, wherein the pixel circuit (PXL) further includes a bias transistor (T9) and a threshold compensation transistor (T3), and wherein the bias transistor (T9) provides a bias signal (VBIAS) to a first electrode of a driving transistor (T1), and the bias signal (VBIAS) is greater than or equal to a first voltage (ELVDD; see Col. 11, Ln. 30-38; Col. 12, Ln. 46-63; Col. 13, Ln. 13-30; and Col. 14, Ln. 63-67 through Col. 15, Ln. 1-11; in combination with Col. 15, Ln. 12-33). It is a goal of Sohn to provide a display device with reduced flicker and variable frame frequency (see Col. 1, Ln. 39-42). Further, Sohn discloses that applying a bias signal, in the manner disclosed by Gao, having a voltage value greater than or equal to the first voltage (VPVDD) can effectively reduce hysteresis on a driving transistor and further reduce a shift in the threshold voltage of the driving transistor, thereby allowing constant current and improved visibility of the display device (again, see Col. 15, Ln. 12-33).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Gao with the teachings of Sohn, such that the bias signal line has the first voltage (VPVDD), as suggested by Sohn, in order to provide effectively reduce hysteresis on the driving transistor and reduce a shift in the threshold voltage of the driving transistor, thereby allowing constant current and improved visibility of the display device.
Claims 6 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Gao in view of Sohn and further in view of Liu et al. (hereinafter “Liu” US 2025 / 0140201).
As pertaining to Claim 6, Gao discloses (see Fig. 15 and Fig. 16 with Fig. 12, Fig. 14, and Fig. 18) that the display panel (100) further includes a plurality of first scan shift circuits (see (7, 8) in Fig. 15) in cascade;
one first scan shift circuit (7) is electrically connected to a gate of one corresponding bias transistor (M7) through a first scan line (Scan2);
the plurality of first scan shift circuits (7, 8) includes a first A scan shift circuit (8);
the first A scan shift circuit (8) is electrically connected to a first A scan start signal line (see (STV_S2));
a first A potential signal line (i.e., a signal line associated with (VGL)) is used to provide an enabling voltage (VGL) of the bias transistor (M7);
the display device further includes a display driving chip (200, 300); and
in the first stage (again, see one cycle time of “Scan1” during (t2) of (T1)), the display driving chip (200, 300) provides an enabling voltage (i.e., a start signal) to the first A scan start signal line (see (STV_S2); see “Specific Implementation” at Page 5, Paragraph [01]; Page 11, Paragraph [05]; Page 12, Paragraph [02]-[03]; and Page 12, Paragraph [07] through Page 13, Paragraph [04]).
While Gao provides an example structural configuration (see Fig. 11) of a shift circuit (4) outputting a light emitting control signal (Emit), neither Gao nor Sohn explicitly provides a structural configuration of a first scan shift circuit. That is, neither Gao nor Sohn discloses that the first A scan shift circuit includes a second A input transistor and a second A output transistor; the second A input transistor is electrically connected between the first A scan start signal line and a gate of the second A output transistor; and a first electrode of the second A output transistor is electrically connected to a first A potential signal line, and a second pole of the second A output transistor is electrically connected to the first scan line; such that in the first stage, the display driving chip provides an enabling voltage of the second A output transistor to the first A scan start signal line.
However, in the same field of endeavor, Liu discloses (see Fig. 8 and Fig. 9) a display panel comprising a pixel circuit structure (100) analogous to that of Gao and Sohn, wherein the display panel includes a plurality of first scan shift circuits (see (Scan-GOA)), with one first scan shift circuit (see (Scan-GOA) in combination with Fig. 9) electrically connected to a gate of one corresponding bias transistor (T1) through a first scan line (see the line connected to the gate of (T1) in Fig. 8); the plurality of first scan shift circuits (again, see (Scan-GOA)) includes a first A scan shift circuit (again, see Fig. 9); the first A scan shift circuit (see Fig. 9) is electrically connected to a first A scan start signal line (STV1); the first A scan shift circuit (again, see Fig. 9) includes a second A input transistor (T9) and a second A output transistor (T19); the second A input transistor (T9) is electrically connected between the first A scan start signal line (STV1) and a gate of the second A output transistor (T19); and a first electrode (i.e., a lower electrode) of the second A output transistor (T19) is electrically connected to a first A potential signal line (VGL), and a second pole (i.e., an upper pole) of the second A output transistor (T19) is electrically connected to the first scan line (see (Out1) corresponding to the line connected to the gate of (T1) in Fig. 8); such that the first A potential signal line (VGL) is used to provide an enabling voltage (VGL) of the bias transistor (T1); and an enabling voltage (VGL) of the second A output transistor (T19) is provided to the first A scan start signal line (STV1; see Page 10, Para. [0120]-[0123] and [0128]; and Page 12 through Page 13, Para. [0149] and [0151]-[0154]). It is a goal of Liu to provide a driving mechanism for a display panel, analogous to that disclosed by Gao and Sohn, that allows for wide-viewing angle, high contrast, fast response speed, and low power consumption (see Page 1, Para. [0003]). Further, in this regard, Liu suggests a first scan shift circuit structure that is known to effectively provide enabling and disabling of a bias transistor with improved flexibility (see Page 8, Para. [0108]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Gao and Sohn with the teachings of Liu, such that the first scan shift circuit of Gao and Sohn has the structural configuration suggested by Liu, in order to effectively provide enabling and disabling of a bias transistor with improved flexibility using a known structure that allows for wide-viewing angle, high contrast, fast response speed, and low power consumption.
As pertaining to Claim 7, Gao discloses (see Fig. 15 and Fig. 16 with Fig. 12, Fig. 14, and Fig. 18) that a second A potential signal line (i.e., a signal line associated with (VGH)) is used to provide a disabling voltage (VGH) of the bias transistor (M7); and
in the first stage (again, see one cycle time of “Scan1” during (t2) of (T1) again, see one cycle time of “Scan1” during (t2) of (T1) again, see one cycle time of “Scan1” during (t2) of (T1) again, see one cycle time of “Scan1” during (t2) of (T1) again, see one cycle time of “Scan1” during (t2) of (T1)), the display driving chip (200, 300) provides a disabling voltage (i.e., see (VGH)) to the second A potential signal line (see (Scan2); again, see “Specific Implementation” at Page 5, Paragraph [01]; Page 11, Paragraph [05]; Page 12, Paragraph [02]-[03]; and Page 12, Paragraph [07] through Page 13, Paragraph [04]).
Liu discloses (see Fig. 8 and Fig. 9) that the first A scan shift circuit (see (Scan-GOA) in combination with Fig. 9) further includes a second A setting transistor (T14); a gate of the second A setting transistor (T14) is electrically connected to a second A control signal line (see a line at (N3) in Fig. 9), a first electrode (i.e., an upper electrode) of the second A setting transistor (T14) is electrically connected to a second A potential signal line (VGH), and a second electrode (i.e., a lower electrode) of the second A setting transistor (T14) is electrically connected to the gate of the second A output transistor (T19); the second A potential signal line (VGH) is used to provide the disabling voltage of the bias transistor (T1); and a disabling voltage (i.e., an off voltage) of the second A setting transistor (T14) is provided to the second A control signal line (see the line at (N3) in Fig. 9; again, see Page 10, Para. [0120]-[0123] and [0128]; and Page 12 through Page 13, Para. [0149] and [0151]-[0154]).
Again, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Gao and Sohn with the teachings of Liu, such that the first scan shift circuit of Gao and Sohn has the structural configuration suggested by Liu, in order to effectively provide enabling and disabling of a bias transistor with improved flexibility using a known structure that allows for wide-viewing angle, high contrast, fast response speed, and low power consumption.
Response to Arguments
Applicant's arguments filed 26 November 2025 have been fully considered but they are not persuasive. The applicant has argued that none of the references relied upon by the examiner, particularly the reference to Gao, teach or fairly suggest the “driving process” of independent Claim 1, wherein “a duration of the first stage is t, and a data refresh frequency of the pixel circuits in the display stage is f, t<=1/f, wherein the 1/f is a duration of a refresh frame or display frame” as newly recited. Specifically, the applicant has asserted that “1/f in the amended claim 1 is not equivalent to T2 in Gao” and that since “T1 in Gao includes both sub-period t1 and sub-period t2, T1 in Gao must be greater than one frame time, which actually teaches away from the amended claim 1” (see Remarks at Pages 16 and 17).
The examiner respectfully points out that the claimed “first stage” is open to broad interpretation and is defined in the claims simply as a “stage” or period that is “located at least before or after the display stage” wherein at some arbitrary time in the “first stage,” “at least one of light-emitting control transistors and driving transistors in each row of pixel circuits is turned off.” The claimed “display stage” is likewise open to broad interpretation. The newly recited “driving process” requires “a data refresh frequency of the pixel circuits in the display stage to be f,” wherein “1/f is a duration of a refresh frame or display frame.” This newly recited feature clarifies that the period “1/f” is not a duration of the claimed “display stage;” rather, the period “1/f” is “a duration of a refresh frame or display frame.” In this regard, Gao clearly discloses a first stage, corresponding to one cycle of “Scan1” during (t2) of (T1) of Figure 14, having a duration of “t,” namely one cycle time of “Scan1” during (t2) of (T1). Gao further discloses that a data refresh frequency, corresponding to a frequency of “Scan1,” of the pixel circuits in the display stage (T2) is f, namely a cycle frequency of “Scan1” during (T2), and that the duration “t,” corresponding to one cycle of “Scan1” during (t2) of (T1), is less than or equal to “1/f,” corresponding to one cycle time of “Scan1” during (T2), wherein the 1/f, corresponding to one cycle time of “Scan1” during (T2), is a duration of a refresh frame or display frame (i.e., one cycle time of “Scan1” during (t2) of (T1) is equal to a cycle time of “Scan1” during (T2)). The examiner respectfully maintains that the invention as recited in at least independent Claim 1 is broad and open to arbitrary interpretation.
Therefore, the rejection of Claims 1, 3 and 5-7 is maintained.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Zhu et al. (US 2019 / 0333596) discloses a shift circuit structure that is relevant to the claimed invention.
Yuan (US 2021 / 0104196) discloses a pixel circuit structure having a bias transistor that is relevant to the claimed invention.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JASON M MANDEVILLE whose telephone number is (571)270-3136. The examiner can normally be reached Mon - Fri 7:30AM-4:00PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chanh Nguyen can be reached at 571-272-7772. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JASON M MANDEVILLE/Primary Examiner, Art Unit 2623