Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 21-40rejected on the ground of nonstatutory double patenting as being unpatentable over claims of U.S. Patent No. 12069805 B2. Although the claims at issue are not identical, they are not patentably distinct from each other because claim mapping below.
Instant Application
21. An integrated circuit package, comprising:at least one printed circuit board having multiple layers; a via passing through at least two layers of the at least one printed circuit board; one or more ground vias positioned around the via; a via contact coupled to an upper end of the via, wherein the via contact is positioned on a top layer of the at least one printed circuit board; a via pad coupled to a lower end of the via, the via pad having a first outer diameter; and a via keepout surrounding the via pad, the via keepout having a second outer diameter that defines a ring-shaped area of electrical isolation area between the via pad and lower ends of the ground vias; and wherein a frequency notch parameter of a signal configured to be transmitted through the via is determined by the first outer diameter of the via pad at the lower end of the via, and wherein a frequency bandwidth parameter for the signal configured to be transmitted through the via is determined by the second outer diameter of the via keepout at the lower end of the via.
22. The integrated circuit package of claim 21, wherein the via includes a signal via having a constant outer diameter through the at least two layers of the at least one printed circuit board and a landing at each of the at least two layers of the at least one printed circuit board.
23. The integrated circuit package of claim 21, wherein the frequency notch is a frequency with a highest return loss in a frequency range for the signal.
24. The integrated circuit package of claim 21, wherein a maximum dimension of the second outer diameter of the via keepout is determined by spacing requirements in the at least one printed circuit board.
25. The integrated circuit package of claim 21, wherein the via pad and the via keepout are positioned in a single layer of the at least one printed circuit board.
26. The integrated circuit package of claim 25, wherein the via pad is coupled to at least one additional via pad in the single layer of the at least one printed circuit board by a stripline.
27. The integrated circuit package of claim 25, wherein the single layer with the via pad and the via keepout is an intermediate layer between the top layer of the at least one printed circuit board and a bottom layer of the at least one printed circuit board.
28. The integrated circuit package of claim 21, further comprising a signal generating integrated circuit package, the signal generating integrated circuit package having a contact coupled to the via contact.
29. The integrated circuit package of claim 28, wherein the signal generating integrated circuit package includes at least one integrated circuit configured to generate the signal configured to be transmitted through the via.
30. An integrated circuit package, comprising:at least one printed circuit board having multiple layers; a via passing through at least two layers of the at least one printed circuit board; one or more ground vias positioned around the via; a via contact coupled to an upper end of the via, wherein the via contact is positioned on a top layer of the at least one printed circuit board; a via pad coupled to a lower end of the via, the via pad having a first outer diameter; and a via keepout surrounding the via pad, the via keepout having a second outer diameter that defines a ring-shaped area of electrical isolation area between the via pad and lower ends of the ground vias; wherein diametric dimensions of the via between the upper end of the via and the lower end of the via are selected to change a first impedance for the via at the upper end of the via to a second impedance for the via at the lower end of the via and at the via pad; wherein the first outer diameter of the via pad at the lower end of the via determines a frequency notch of a signal configured to be transmitted through the via; and wherein the second outer diameter of the via keepout at the lower end of the via determines a frequency bandwidth for the signal configured to be transmitted through the via.
31. The integrated circuit package of claim 30, wherein the via includes a signal via through the at least two layers of the at least one printed circuit board and a landing at each of the at least two layers of the at least one printed circuit board, and wherein the diametric dimensions of the via include outer diameters of the signal via and the landings.
32. The integrated circuit package of claim 30, wherein the via pad is coupled to at least one additional via in the at least one printed circuit board by a stripline.
33. The integrated circuit package of claim 30, wherein the frequency notch is selected to be within the frequency bandwidth.
34. The integrated circuit package of claim 33, further comprising a signal generating integrated circuit package, the signal generating integrated circuit package having a contact coupled to the via contact.
35. The integrated circuit package of claim 34, wherein the at least one printed circuit board includes at least two printed circuit boards stacked together and coupled to the signal generating integrated circuit package, the via passing through at least one layer of each of the at least two printed circuit boards with the via contact coupled to the contact of the signal generating integrated circuit package.
36. The integrated circuit package of claim 35, further comprising a terminal region at a junction between the at least two printed circuit boards, wherein the terminal region provides a transition between a portion of the via in a first of the at least two printed circuit boards and a portion of the via in a second of the at least two printed circuit boards.
37. The integrated circuit package of claim 36, further comprising a terminal positioned in the terminal region, wherein the terminal connects the portion of the via in the first of the at least two printed circuit boards and the portion of the via in the second of the at least two printed circuit boards.
38. An integrated circuit package, comprising:a substrate having multiple layers; a plurality of vias passing through at least two layers of the substrate; a plurality of ground vias positioned around the vias; a plurality of via contacts coupled to upper ends of the vias, wherein the via contacts are positioned on a top layer of the substrate; a plurality of via pads coupled to lower ends of the vias, the via pads having first outer diameters; and a plurality of via keepouts surrounding the via pads, the via keepouts having second outer diameters that define ring-shaped areas of electrical isolation area between the via pads and lower ends of the ground vias; wherein frequency notch parameters of signals configured to be transmitted through the vias are determined by the first outer diameters of the via pads at the lower ends of the vias, and wherein frequency bandwidth parameters for the signals configured to be transmitted through the vias are determined by the second outer diameters of the via keepouts at the lower ends of the vias.
39. The integrated circuit package of claim 38, further comprising a signal generating integrated circuit package, the signal generating integrated circuit package having a plurality of contacts coupled to the via contacts, and wherein the signal generating integrated circuit package includes at least one integrated circuit configured to generate the signal configured to be transmitted through the vias.
40. The integrated circuit package of claim 38, further comprising a connector package, the connector package having a plurality of contacts coupled to the via contacts.
US Patent 12069805 B2
1. An integrated circuit package, comprising: at least one printed circuit board having multiple layers; a via passing through at least two layers of the at least one printed circuit board; one or more ground vias positioned around the via; a via contact coupled to an upper end of the via, wherein the via contact is positioned on a top layer of the at least one printed circuit board; a via pad coupled to a lower end of the via, the via pad having a first outer diameter; a via keepout surrounding the via pad, the via keepout having a second outer diameter that defines a ring-shaped area of electrical isolation area between the via pad and lower ends of the ground vias; and a stripline coupled to the via pad; wherein an impedance of the via at the via pad approximately matches an impedance of the stripline, the impedance of the via at the via pad being determined by dimensions of the via between the upper end of the via and the lower end of the via; and wherein a frequency notch parameter of a signal configured to be transmitted through the via and the stripline is determined by the first outer diameter of the via pad at the lower end of the via, and wherein a frequency bandwidth parameter for the signal configured to be transmitted through the via and the stripline is determined by the second outer diameter of the via keepout at the lower end of the via.
2. The integrated circuit package of claim 1, wherein the via includes a signal via having a constant outer diameter through the at least two layers of the at least one printed circuit board and a landing at each of the at least two layers of the at least one printed circuit board, and wherein the dimensions of the via selected to provide the impedance for the via at the via pad include the outer diameter of the signal via and outer diameters of the landings.
3. The integrated circuit package of claim 1, wherein the frequency notch is a frequency with a highest return loss in a frequency range for the signal.
4. The integrated circuit package of claim 1, wherein a maximum dimension of the second outer diameter of the via keepout is determined by spacing requirements in the at least one printed circuit board.
5. The integrated circuit package of claim 1, wherein the via pad, the stripline, and the via keepout are positioned in a single layer of the at least one printed circuit board.
6. The integrated circuit package of claim 5, wherein the stripline is coupled to at least one additional via pad in the single layer of the at least one printed circuit board.
7. The integrated circuit package of claim 5, wherein the single layer with the via pad, the stripline, and the via keepout is an intermediate layer between the top layer of the at least one printed circuit board and a bottom layer of the at least one printed circuit board.
8. An integrated circuit package, comprising: at least one printed circuit board having multiple layers; a via passing through at least two layers of the at least one printed circuit board; one or more ground vias positioned around the via; a via contact coupled to an upper end of the via, wherein the via contact is positioned on a top layer of the at least one printed circuit board; a via pad coupled to a lower end of the via, the via pad having a first outer diameter; a via keepout surrounding the via pad, the via keepout having a second outer diameter that defines a ring-shaped area of electrical isolation area between the via pad and lower ends of the ground vias; and a stripline coupled to the via pad in the at least one printed circuit board; wherein diametric dimensions of the via between the upper end of the via and the lower end of the via are selected to change a first impedance for the via at the upper end of the via to a second impedance for the via at the lower end of the via and at the via pad, wherein the second impedance at the lower end of the via approximately matches an impedance of the stripline; wherein the first outer diameter of the via pad at the lower end of the via determines a frequency notch of a signal configured to be transmitted through the via and the stripline; and wherein the second outer diameter of the via keepout at the lower end of the via determines a frequency bandwidth for the signal configured to be transmitted through the via and the stripline.
9. The integrated circuit package of claim 8, wherein the via includes a signal via through the at least two layers of the at least one printed circuit board and a landing at each of the at least two layers of the at least one printed circuit board, and wherein the diametric dimensions of the via include outer diameters of the signal via and the landings.
10. The integrated circuit package of claim 8, wherein the stripline is coupled to at least one additional via in the at least one printed circuit board.
11. The integrated circuit package of claim 8, wherein the frequency notch is selected to be within the frequency bandwidth.
12. The integrated circuit package of claim 8, further comprising a signal generating integrated circuit package, the signal generating integrated circuit package having a contact coupled to the via contact.
13. The integrated circuit package of claim 12, wherein the signal generating integrated circuit package includes at least one integrated circuit configured to generate the signal configured to be transmitted through the via and the stripline.
14. The integrated circuit package of claim 13, wherein the via changes an impedance of the at least one integrated circuit at the via pad to the impedance of the stripline.
15. An integrated circuit package, comprising: at least one printed circuit board having multiple layers; a plurality of vias passing through at least two layers of the at least one printed circuit board; a plurality of ground vias positioned around the vias; a plurality of via contacts coupled to upper ends of the vias, wherein the via contacts are positioned on a top layer of the at least one printed circuit board; a plurality of via pads coupled to lower ends of the vias, the via pads having first outer diameters; a plurality of via keepouts surrounding the via pads, the via keepouts having second outer diameters that define ring-shaped areas of electrical isolation area between the via pads and lower ends of the ground vias; and a plurality of striplines coupled to the via pads in the at least one printed circuit board; wherein diametric dimensions of the vias between the upper end of the via and the lower end of the via are selected to provide impedances for the vias at the via pads that substantially match impedances of the striplines; and wherein the first outer diameters at the lower end of the vias determine a frequency notch of a signal configured to be transmitted through the vias and the striplines, and wherein the second outer diameters at the lower end of the vias determine a frequency bandwidth of the signal configured to be transmitted through the vias and the striplines.
16. The integrated circuit package of claim 15, further comprising a signal generating integrated circuit package, the signal generating integrated circuit package having a plurality of contacts coupled to the via contacts, and wherein the signal generating integrated circuit package includes at least one integrated circuit configured to generate the signal configured to be transmitted through the vias and the striplines.
17. The integrated circuit package of claim 15, further comprising a connector package, the connector package having a plurality of contacts coupled to the via contacts.
18. The integrated circuit package of claim 12, wherein the at least one printed circuit board includes at least two printed circuit boards stacked together and coupled to the signal generating integrated circuit package, the via passing through at least one layer of each of the at least two printed circuit boards with the via contact coupled to the contact of the signal generating integrated circuit package.
19. The integrated circuit package of claim 18, further comprising a terminal region at a junction between the at least two printed circuit boards, wherein the terminal region provides a transition between a portion of the via in a first of the at least two printed circuit boards and a portion of the via in a second of the at least two printed circuit boards.
20. The integrated circuit package of claim 19, further comprising a terminal positioned in the terminal region, wherein the terminal connects the portion of the via in the first of the at least two printed circuit boards and the portion of the via in the second of the at least two printed circuit boards.
Allowable Subject Matter
Claims 21-40 are objected to as being dependent upon a rejected base claim, but would be allowable if double patenting rejection is overcome above.
The prior art made of record and not relied upon is considered pertinent toapplicant's disclosure.
Palotto et al. (US 11289802 B2) discloses a a impedance matching structure..
Curtis (US 2020/0211986 A1) discloses a RF structure.
Cjamdra et al. (US 2019/0208632 A1) discloses a steeped via structure.
.
Therefore, prior art of record neither anticipates nor renders obvious the instantapplication claimed invention as a whole either taken alone or in combination.
Any comments considered necessary by applicant must be submitted no laterthan the payment of the issue fee and, to avoid processing delays, should preferablyaccompany the issue fee. Such submissions should be clearly labeled "Comments onStatement of Reasons for Allowance."
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PETE LEE whose telephone number is (571) 270-5921. The examiner can normally be reached on Monday-Friday (2nd & 4th Friday Off). If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Timothy Dole can be reached at (571) 272-2229 The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free).
/PETE T LEE/Primary Examiner, Art Unit 2847
Prosecution Insights