Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Claims 1-30 have been cancelled, and Claims 31-50 have been added. Claims 31-50 are currently pending.
Applicant’s arguments, filed 07/13/2026, in light of Applicant elected species 1 (Fig. 2) which encompasses new claims 31-50 have been fully considered and are moot in view of the new rejection (see infra).
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory obviousness-type double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the conflicting application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement.
Effective January 1, 1994, a registered attorney or agent of record may sign a terminal disclaimer. A terminal disclaimer signed by the assignee must fully comply with 37 CFR 3.73(b).
Regarding Claims 31-32, 35, 44 and 45, are rejected on the ground of nonstatutory obviousness-type double patenting as being unpatentable respectively over claims 1&5, 2, 12 and 17 of U.S. Patent No. 10728475 B2 as depicted in the Table below. Although the conflicting claims are not identical, they are not patentably distinct from each other because claims 31-32, 35, 44 and 45 of the instant application are broader in scope and are obviousness over respectively claims 1&5, 2, 12 and 17 of U.S. Patent 10728475 B2, in that claims 1&5, 2, 12 and 17 of the U.S. Patent contain all the limitations of claims 31-32, 35, 44 and 45 of the instant application. Claims 31-32, 35, 44 and 45 of the instant application are therefore not patently distinct from the earlier U.S. Patent claim and such is unpatentable for obvious-type double patenting.
Claim 44 is rejected under nonstatutory obviousness-type double patenting as being unpatentable over claim 12 of the US 10728475 B2 patent as applied below (see table below), in view of Taura (US 2010/0225776 A1, hereafter “Taura”).
Regarding claim 44, are rejected under nonstatutory obviousness-type double patenting as being unpatentable over the US 10728475 B2, except a signal processing circuit.
However, Taura discloses an electronic apparatus, comprising: a signal processing circuit; and a light detecting device (Fig. 16, [0135]-[0137]&[0144]: an electronic apparatus comprising a signal processing circuit 213 and a solid-state imaging device 1).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate an electronic apparatus, comprising: a signal processing circuit as taught by Taura into the 10728475 B2. The suggestion/ motivation for doing so would be to image processing.
Instant Application (18/774505)
US 10728475 B2
31. (New) A light detecting device, comprising:
a photoelectric converter disposed in a semiconductor substrate;
a first transistor configured to transfer charge generated in the photoelectric converter;
a floating diffusion region disposed in the semiconductor substrate to and store the charge transferred by the first transistor, the floating diffusion region having a predetermined storage capacitance;
a second transistor to convert the charge stored in the floating diffusion region to a pixel signal;
and a wiring layer disposed on a surface of the semiconductor substrate
and comprising first wiring that electrically connects the floating diffusion region and a gate electrode of the second transistor,
wherein, in a plan view, the first wiring does not overlap with a gate electrode of the first transistor.
1. An imaging element comprising:
a pixel including: a semiconductor substrate; a photoelectric conversion portion disposed in the semiconductor substrate
a first transfer transistor configured to transfer the charge generated in the photoelectric conversion portion;
a floating diffusion to which the charge is transferred through the first transfer transistor, the floating diffusion having a predetermined storage capacitance;
an amplification transistor configured to output a pixel signal based on the charge transferred from the floating diffusion;
and including connection wiring, contact wiring and other wiring;
wherein the connection wiring is connected to the floating diffusion and the amplification transistor through first and second portions of the contact wiring,
5. The imaging element according to claim 1, wherein the connection wiring is laid out by avoiding overlap with a gate electrode of the first transfer transistor in the plan view, and wherein the insulating layer contacts the floating diffusion.
32. The light detecting device of claim 31, further comprising: at least one third transistor coupled to the first transistor and the second transistor.
35. The light detecting device of claim 32, wherein the at least one third transistor is controllable to change the storage capacitance of the floating diffusion.
2. The imaging element according to claim 1, wherein the second transfer transistor is configured to switch a storage capacitance for accumulating the charge converted by the amplification transistor to the pixel signal,
2. The imaging element according to claim 1, wherein the second transfer transistor is configured to switch a storage capacitance for accumulating the charge converted by the amplification transistor to the pixel signal,
44. An electronic apparatus, comprising: a signal processing circuit; and a light detecting device, comprising:
a photoelectric converter disposed in a semiconductor substrate;
a first transistor configured to transfer charge generated in the photoelectric converter;
a floating diffusion region disposed in the semiconductor substrate and to store the charge transferred by the first transistor, the floating diffusion region having a predetermined storage capacitance;
a second transistor to convert the charge stored in the floating diffusion region to a pixel signal;
and a wiring layer disposed on a surface of the semiconductor substrate and comprising first wiring that electrically connects the floating diffusion region and a gate electrode of the second transistor,
wherein, in a plan view, the first wiring does not overlap with a gate electrode of the first transistor.
45. (New) The light detecting device of claim 44, further comprising: at least one third transistor coupled to the first transistor and the second transistor.
12. An electronic device comprising: an imaging element including
a pixel including: a semiconductor substrate; a photoelectric conversion portion disposed in the semiconductor substrate and configured to convert incident light to a charge by photoelectric conversion and accumulate the charge;
a first transfer transistor configured to transfer the charge generated in the photoelectric conversion portion;
a floating diffusion to which the charge is transferred through the first transfer transistor, the floating diffusion having a predetermined storage capacitance;
an amplification transistor configured to output a pixel signal based on the charge transferred from the floating diffusion;
and including a connection wiring, contact wiring, and other wiring;
17. The imaging element according to claim 13, wherein the connection wiring is laid out by avoiding overlap with a gate electrode of the first transfer transistor in the plan view.
12…. a second transfer transistor coupled between the floating diffusion and the reset transistor…
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 31-43 and 48-50 are rejected under 35 U.S.C. 102(a)(1) as being anticipated over the Korean application KR 20100077986 A to LIM GUN HYUK (employing the provided machine translation and hereafter “LIM”).
Regarding claim 31, LIM teaches a light detecting device (Figs. 4-6, [0015]: a 4T type image sensor), comprising:
a photoelectric converter disposed in a semiconductor substrate (as illustrated by Figs. 4 or 5 and 6, [0017]: a photodiode 100, 130 or 132 occupies the largest area in the active area, senses incident light, and generates charge according to the detected amount of light. The photodiode on a semiconductor substrate 200);
a first transistor configured to transfer charge generated in the photoelectric converter (as illustrated by Figs. 4 or 5 and 6, [0016]: a transfer transistor (Tx, Tx1, Tx2));
a floating diffusion region disposed in the semiconductor substrate to and store the charge transferred by the first transistor, the floating diffusion region having a predetermined storage capacitance (as illustrated by Figs. 4 or 5 and 6, [0018]: The transfer transistor Tx serves to transport charges generated in the photodiodes 100, 130, and 132 to floating diffusion regions FD 120 and 134);
a second transistor to convert the charge stored in the floating diffusion region to a pixel signal (as illustrated by Figs. 4 or 5 and 6, [0020]: drive transistor Dx serves as a source follower for converting charges into a voltage signal);
and a wiring layer disposed on a surface of the semiconductor substrate and comprising first wiring that electrically connects the floating diffusion region and a gate electrode of the second transistor (as illustrated by Figs. 4 or 5 and 6, [0026]: first metal wire 230 (corresponds to the metal wire 112 or 154)), wherein, in a plan view, the first wiring does not overlap with a gate electrode of the first transistor (as illustrated by Figs. 4 or 5 and 6, [0027]: the first metal wire 230 do not overlap with the transfer transistor (Tx, Tx1, Tx2) gate).
Regarding claim 32, LIM teaches the light detecting device of claim 31, in addition LIM discloses further comprising: at least one third transistor coupled to the first transistor and the second transistor (as illustrated by Figs. 4 or 5 and 6, [0016]: reset transistor (Rx) between the transfer transistor (Tx, Tx1, Tx2) and the drive transistor Dx).
Regarding claim 33, LIM teaches the light detecting device of claim 32, in addition LIM discloses wherein the first wiring does not overlap with a gate electrode of each of the at least one third transistor (as illustrated by Figs. 4 or 5 and 6, [0026]: the first metal wire 230 (corresponds to the metal wire 112 or 154) do not overlap with the reset transistor (Rx)).
Regarding claim 34, LIM teaches the light detecting device of claim 32, in addition LIM discloses wherein the floating diffusion region is electrically connected between the second transistor and the at least one third transistor (as illustrated by Figs. 4 or 5 and 6, [0018]: the floating diffusion regions FD 120 and 134 coupled between the drive transistor Dx and the reset transistor (Rx)).
Regarding claim 35, LIM teaches the light detecting device of claim 32, in addition LIM discloses wherein the at least one third transistor is controllable to change the storage capacitance of the floating diffusion (as illustrated by Figs. 4 or 5 and 6, [0018]-[0019]: the reset transistor Rx serves to discharge charge stored in the floating diffusion regions FD 120 and 134 for signal detection. The floating diffusion regions FD 120 and 134 are set to a predetermined low charge state by turning on the reset transistor Rx for electrons from the photodiodes 100, 130 and 132 before transportation.).
Regarding claim 36, LIM teaches the light detecting device of claim 31, in addition LIM discloses wherein the wiring layer further comprises: a second wiring electrically connected to a gate electrode of the first transistor (as illustrated by Figs. 4 or 5 and 6, [0027]&[0045]: a second metal wire 250 connected to the gate electrode 210 of the transfer transistor (Tx, Tx1, Tx2)).
Regarding claim 37, LIM teaches the light detecting device of claim 36, in addition LIM discloses wherein the second wiring is to drive the first transistor (as illustrated by Figs. 4 or 5 and 6, [0027]&[0045]: the second metal wire 250 connected to the gate electrode 210 is to drive the transfer transistor (Tx, Tx1, Tx2)).
Regarding claim 38, LIM teaches the light detecting device of claim 37, in addition LIM discloses wherein the second wiring is to output the pixel signal (as illustrated by Figs. 4 or 5 and 6, [0027]&[0045]: the second metal wire 250 connected to the gate electrode 210 is to drive the transfer transistor (Tx, Tx1, Tx2. The transfer transistor (Tx, Tx1, Tx2) serves to transport charges generated in the photodiodes 100, 130, and 132 to the floating diffusion regions FD 120 and 134.).
Regarding claim 39, LIM teaches the light detecting device of claim 36, in addition LIM discloses wherein the first wiring is closer to the surface of the semiconductor substrate than the second wiring in a cross-sectional view (as illustrated by Fig. 6: the first metal wire 230 (corresponds to the metal wire 112 or 154) closer to the to the surface of the semiconductor substrate 200 than that of the second metal wire 250).
Regarding claim 39, LIM teaches the light detecting device of claim 31, in addition LIM discloses wherein the gate electrode of the second transistor is disposed on the semiconductor substrate (as illustrated by Fig. 6, [0025]: a second gate electrode 208 of the driver transistor Dx is formed on the semiconductor substrate 200).
Regarding claim 41, LIM teaches the light detecting device of claim 40, in addition LIM discloses wherein a gate electrode of the first transistor is disposed on the semiconductor substrate (as illustrated by Fig. 6, [0023]: first gate electrode 210 of the transfer transistor Tx is formed on the semiconductor substrate 200).
Regarding claim 42, LIM teaches the light detecting device of claim 41, in addition LIM discloses wherein, in a cross-sectional view, the floating diffusion region is located between the gate electrode of the first transistor and the gate electrode of the second transistor (as illustrated by Fig. 6: the floating diffusion region FD between the first gate electrode 210 of the transfer transistor Tx and second gate electrode 208 of the driver transistor Dx).
Regarding claim 43, LIM teaches the light detecting device according to claim 41, in addition LIM discloses wherein, in the plan view, the first transistor and the second transistor are at a same side of the photoelectric converter (as illustrated by Figs. 4 or 5 and 6: the transfer transistor Tx and the driver transistor Dx are at the same side of the photodiodes 100, 130, and 132).
Regarding claim 48, claim 48 has been analyzed with regard to claims 36-38 and is rejected for the same reasons as used above.
Regarding claims 49-50, claims 49-50 have been analyzed with regard to respective claims 32-33 and are rejected for the same reasons as used above.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 44-47 are rejected under 35 U.S.C. 103 as being unpatentable over Korean application KR 20100077986 A to LIM GUN HYUK (employing the provided machine translation and hereafter “LIM”), in view of Taura (US 2010/0225776 A1, hereafter “Taura”).
Regarding claim 44, claim 44 has been analyzed and rejected with regard to claim 31, except further teaching on: an electronic apparatus, comprising: a signal processing circuit.
However, Taura discloses an electronic apparatus, comprising: a signal processing circuit; and a light detecting device (Fig. 16, [0135]-[0137]&[0144]: an electronic apparatus comprising a signal processing circuit 213 and a solid-state imaging device 1).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate an electronic apparatus, comprising: a signal processing circuit as taught by Taura employing the LIM’s image sensor. The suggestion/ motivation for doing so would be to provide an image sensor and a method of manufacturing the same that can be reduced to improve the sensitivity (LIM: [0013]).
Regarding claims 45-47, claims 45-47 have been analyzed with regard to respective claims 32-34 and are rejected in view of LIM and for the same reasons as used above.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Contact
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ABDELAAZIZ TISSIRE whose telephone number is (571)270-7204. The examiner can normally be reached on Monday through Friday from 8 AM to 5 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ye Lin can be reached on 571-272-7372. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ABDELAAZIZ TISSIRE/ Primary Examiner, Art Unit 2638
