Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (lDS) submitted are in compliance with the provisions of 37 CFR 1.97 and have been considered by the Examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory obviousness-type double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the conflicting application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement.
Effective January 1, 1994, a registered attorney or agent of record may sign a terminal disclaimer. A terminal disclaimer signed by the assignee must fully comply with 37 CFR 3.73(b).
Regarding Claims 1-8, 9 and 10,are rejected on the ground of nonstatutory obviousness-type double patenting as being unpatentable respectively over claims 1-8, 11 and 12 of U.S. Patent No. 10728475 B2 as depicted in the Table below. Although the conflicting claims are not identical, they are not patentably distinct from each other because claims 1-8, 9 and 10 of the instant application are broader in scope and are obviousness over respectively claims 1-8, 11 and 12 of U.S. Patent 10728475 B2, in that claims 1-8, 11 and 12 of the U.S. Patent contain all the limitations of claims 1-8, 9 and 10 of the instant application. Claims 1-8, 9 and 10 of the instant application are therefore not patently distinct from the earlier U.S. Patent claim and such is unpatentable for obvious-type double patenting.
Claims 1, 9 and 10 are rejected under nonstatutory obviousness-type double patenting as being unpatentable over claims 1, 11 and 12 of the US 10728475 B2 patent as applied below (see table below), in view of Taura (US 2010/0225776 A1, hereafter “Taura”).
Regarding claims 1, 9 and 10, are rejected under nonstatutory obviousness-type double patenting as being unpatentable over the US 10728475 B2, except the contact wiring extending in a vertical direction with respect to a semiconductor substrate.
However, Taura discloses the contact wiring extending in a vertical direction with respect to a semiconductor substrate (as illustrated in Fig. 6, [0060]&[0067]: the bottom wiring layer M0 disposed on a first insulating layer 27 is connected to the gate electrode 22 of the amplification transistor Tr3 via a contact portion 36 (“vertical”), and is electrically connected to the floating diffusion 15 by a contact portion 25).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the contact wiring extending in a vertical direction with respect to a semiconductor substrate as taught by Taura into the 10728475 B2. The suggestion/ motivation for doing so would be to allow electrical contact and transfer of data between stacked substrates.
Instant Application (18/774505)
US 10728475 B2
1. An imaging element comprising:
a pixel including
a photoelectric conversion portion configured to convert incident light to a charge by photoelectric conversion and accumulate the charge,
a charge transfer unit configured to transfer the charge generated in the photoelectric conversion portion,
a diffusion layer to which the charge is transferred through the charge transfer unit, the diffusion layer having a predetermined storage capacitance,
a conversion unit configured to convert the charge transferred to the diffusion layer to a pixel signal,
and connection wiring configured to connect the diffusion layer and the conversion unit,
wherein the connection wiring is connected to the diffusion layer and the conversion unit through contact wiring
and is formed closer to the semiconductor substrate than other wiring provided in the pixel.
1. An imaging element comprising:
a pixel including:
a photoelectric conversion portion
a first transfer transistor configured to transfer the charge generated in the photoelectric conversion portion;
a floating diffusion to which the charge is transferred through the first transfer transistor, the floating diffusion having a predetermined storage capacitance;
an amplification transistor configured to output a pixel signal based on the charge transferred from the floating diffusion;
and including connection wiring, contact wiring and other wiring;
wherein the connection wiring is connected to the floating diffusion and the amplification transistor through first and second portions of the contact wiring,
wherein the connection wiring is closer to the semiconductor substrate than the other wiring
2. The imaging element according to claim 1, wherein the pixel further includes a switching unit configured to switch a storage capacitance for accumulating the charge converted by the conversion unit to the pixel signal.
3. The imaging element according to claim 1, further comprising: a driving unit configured to set conversion efficiency in the transfer transistor to a high conversion rate and perform reading-out of the pixel signal by switching the storage capacitance to a large capacitance by the switching unit, and set the conversion efficiency in the transfer transistor to a low conversion rate and perform reading-out of the pixel signal by switching the storage capacitance to a small capacitance by the switching unit.
4. The imaging element according to claim 1, wherein the connection wiring is formed as a film thinner than the other wiring provided in the pixel.
5. The imaging element according to claim 1, wherein the connection wiring is laid out by avoiding overlap with a gate electrode of a transistor provided in the pixel in a plan view.
6. The imaging element according to claim 1, wherein the connection wiring includes titanium, titanium nitride, tungsten, aluminum or copper or a lamination structure of titanium and titanium nitride.
7. The imaging element according to claim 1, wherein the pixel includes a plurality of photoelectric conversion portions having sensitivities different from each other.
8. The imaging element according to claim 7, further comprising: a driving unit configured to sequentially transfer pixel signals corresponding to charges generated in the plurality of respective photoelectric conversion portions to the diffusion layer and perform reading-out of the pixel signals.
2. The imaging element according to claim 1, wherein the second transfer transistor is configured to switch a storage capacitance for accumulating the charge converted by the amplification transistor to the pixel signal,
3. The imaging element according to claim 1, further comprising: a driving circuit configured to set conversion efficiency to a high conversion rate and perform reading-out of the pixel signal by switching the storage capacitance to a large capacitance using the second transfer transistor, and set the conversion efficiency to a low conversion rate and perform reading-out of the pixel signal by switching the storage capacitance to a small capacitance using the second transfer transistor.
4. The imaging element according to claim 1, wherein the connection wiring is thinner than the other wiring,
5. The imaging element according to claim 1, wherein the connection wiring is laid out by avoiding overlap with a gate electrode of the first transfer transistor in the plan view, and wherein the insulating layer contacts the floating diffusion.
6. The imaging element according to claim 1, wherein the connection wiring includes titanium, titanium nitride, tungsten, aluminum, or copper, or a lamination structure of titanium and titanium nitride,
7. The imaging element according to claim 1, wherein the pixel includes a plurality of photoelectric conversion portions having sensitivities different from each other.
8. The imaging element according to claim 7, further comprising: a driving circuit configured to sequentially transfer pixel signals corresponding to charges generated in the plurality of photoelectric conversion portions to the floating diffusion and perform reading-out of the pixel signals.
9. A driving method of an imaging element including a pixel including a photoelectric conversion portion configured to convert incident light to a charge by photoelectric conversion and accumulate the charge,
a charge transfer unit configured to transfer the charge generated in the photoelectric conversion portion,
a diffusion layer to which the charge is transferred through the charge transfer unit, the diffusion layer having a predetermined storage capacitance,
a conversion unit configured to convert the charge transferred to the diffusion layer to a pixel signal,
connection wiring configured to connect the diffusion layer and the conversion unit,
and a switching unit configured to switch a storage capacitance for accumulating the charge converted by the conversion unit to the pixel signal,
the connection wiring being connected to the diffusion layer and the conversion unit through contact wiring
being formed closer to the semiconductor substrate than other wiring provided in the pixel,
the driving method comprising: setting conversion efficiency in the transfer transistor to a high conversion rate and performing reading-out of the pixel signal by switching the storage capacitance to a large capacitance by the switching unit; and setting the conversion efficiency in the transfer transistor to a low conversion rate and performing reading-out of the pixel signal by switching the storage capacitance to a small capacitance by the switching unit.
11. A driving method of an imaging element, the imaging element including a pixel, the pixel including a semiconductor substrate, a photoelectric conversion portion disposed in the semiconductor substrate and configured to convert incident light to a charge by photoelectric conversion and accumulate the charge,
a first transfer transistor configured to transfer the charge generated in the photoelectric conversion portion,
a floating diffusion to which the charge is transferred through the first transfer transistor,
an amplification transistor configured to output a pixel signal based on the charge transferred from the floating diffusion layer,
a reset transistor configured to reset the floating diffusion during a reset operation for the pixel, a second transfer transistor coupled between the floating diffusion and the reset transistor, an insulating layer on the semiconductor substrate and including
a connection wiring, contact wiring, and other wiring,
an insulating film positioned between the insulating layer and the semiconductor substrate,
wherein the second transfer transistor is configured to switch a storage capacitance for accumulating the charge converted by the amplification transistor,
the connection wiring being connected to the floating diffusion and the amplification transistor through first and second portions of the contact wiring,
wherein the connection wiring is closer to the semiconductor substrate than the other wiring
within the insulting layer, the floating diffusion having a predetermined storage capacitance, wherein, in a plan view, the gate of the amplification transistor is spaced apart from the photoelectric conversion portion in a first direction, wherein, in the plan view, a gate of the reset transistor is spaced apart from the photoelectric conversion portion in the first direction and spaced apart from the gate of the amplification transistor in a second direction perpendicular to the first direction, wherein, in the plan view, a gate of the second transfer transistor is spaced apart from the photoelectric conversion portion in the first direction and spaced apart from the gate of the amplification transistor in the second direction, and wherein, in the plan view, the connection wiring extends from the floating diffusion to the gate of the amplification transistor in a third direction that is between the first direction and the second direction,
the driving method comprising: setting conversion efficiency to a high conversion rate and performing reading-out of the pixel signal by switching the storage capacitance to a large capacitance using the second transfer transistor; and setting the conversion efficiency to a low conversion rate and performing reading-out of the pixel signal by switching the storage capacitance to a small capacitance using the second transfer transistor.
10. An electronic device comprising: an imaging element including a pixel including a photoelectric conversion portion configured to convert incident light to a charge by photoelectric conversion and accumulate the charge,
a charge transfer unit configured to transfer the charge generated in the photoelectric conversion portion,
a diffusion layer to which the charge is transferred through the charge transfer unit, the diffusion layer having a predetermined storage capacitance,
a conversion unit configured to convert the charge transferred to the diffusion layer to a pixel signal,
and connection wiring configured to connect the diffusion layer and the conversion unit, wherein the connection wiring is connected to the diffusion layer
on which the diffusion layer is formed
and is formed closer to the semiconductor substrate than other wiring provided in the pixel.
12. An electronic device comprising: an imaging element including a pixel including: a semiconductor substrate; a photoelectric conversion portion disposed in the semiconductor substrate and configured to convert incident light to a charge by photoelectric conversion and accumulate the charge;
a first transfer transistor configured to transfer the charge generated in the photoelectric conversion portion;
a floating diffusion to which the charge is transferred through the first transfer transistor, the floating diffusion having a predetermined storage capacitance;
an amplification transistor configured to output a pixel signal based on the charge transferred from the floating diffusion;
a reset transistor configured to reset the floating diffusion during a reset operation for the pixel; a second transfer transistor coupled between the floating diffusion and the reset transistor; an insulating layer on the semiconductor substrate
and including a connection wiring, contact wiring, and other wiring;
wherein the connection wiring is closer to the semiconductor substrate than the other wiring within the insulating layer,
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are: charge transfer unit, conversion unit, switching unit, and driving unit, in claims 1-3, 8 and 10. the method of claim 9 similarly recites the same features.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 3 recites the limitation " to set conversion efficiency in the transfer transistor" in line 2. There is insufficient antecedent basis for this limitation in the claim.
Claim 9 recites the limitation " setting conversion efficiency in the transfer transistor" in line 15. There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 4, 6 and 10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Taura (US 2010/0225776 A1, hereafter “Taura”).
Regarding claim 1, Taura teaches an imaging element (Figs. 1-6) comprising:
a pixel including a photoelectric conversion portion configured to convert incident light to a charge by photoelectric conversion and accumulate the charge (Figs. 4&5, [0053]: photodetector 14 formed of a photodiode disposed at a predetermined position on the upper surface of a substrate 13 made of silicon. The photodetector 14 generates signal charge corresponding to the quantity of incident light and accumulates the signal charge.),
a charge transfer unit configured to transfer the charge generated in the photoelectric conversion portion (Figs. 4&6, [0056]: transfer transistor Tr1 is driven by a transfer pulse ØTRG to transfer the electric charges generated in the photodetector 14),
a diffusion layer to which the charge is transferred through the charge transfer unit, the diffusion layer having a predetermined storage capacitance (Figs. 4&6, [0054]: floating diffusion 15 is disposed on the upper surface of the substrate 13 at a position adjacent the photodetector 14. The region between the photodetector 14 and the floating diffusion 15 serves as a channel region of the transfer transistor Tr1 (temporarily accumulates electric charges)),
a conversion unit configured to convert the charge transferred to the diffusion layer to a pixel signal (Figs. 4&6, [0058]: amplification transistor Tr3 functions as a source follower, and the potential of the floating diffusion 15 is supplied to the gate electrode 22 of the amplification transistor Tr3.),
and connection wiring configured to connect the diffusion layer and the conversion unit (Fig. 6, [0067]: a bottom wiring layer M0 is disposed on a first insulating layer 27 at a region above the floating diffusion 15, and is used as a wire for connecting the floating diffusion 15 and the gate electrode 22 of the amplification transistor Tr3), wherein the connection wiring is connected to the diffusion layer and the conversion unit through contact wiring extending in a vertical direction with respect to a semiconductor substrate on which the diffusion layer is formed and is formed closer to the semiconductor substrate than other wiring provided in the pixel (as illustrated in Fig. 6, [0060]&[0067]: the bottom wiring layer M0 disposed on a first insulating layer 27 is connected to the gate electrode 22 of the amplification transistor Tr3 via a contact portion 36, and is electrically connected to the floating diffusion 15 by a contact portion 25).
Regarding claim 4, Taura teaches the imaging element according to claim 1, in addition Taura discloses wherein the connection wiring is formed as a film thinner than the other wiring provided in the pixel (as illustrated in Fig.6, the thickness of wiring layer M0 is thinner that of wiring layers M1-M3).
Regarding claim 6, Taura teaches the imaging element according to claim 1, in addition Taura discloses wherein the connection wiring includes titanium, titanium nitride, tungsten, aluminum or copper or a lamination structure of titanium and titanium nitride (Fig. 6, [0060]: For the bottom wiring layer M0, a metal such as tungsten, aluminum, and copper may be used).
Regarding claim 10, claim 10 has been analyzed and rejected with regard to claim 1 and in accordance with Taura's further teaching on: an electronic device 200 comprising the solid-state imaging device (Fig. 16, [0144]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2, 3 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Taura (US 2010/0225776 A1, hereafter “Taura”), in view of Mabuchi (US 2013/0033631 A1, hereafter “Mabuchi”).
Regarding claim 2, Taura teaches the imaging element according to claim 1, except wherein the pixel further includes a switching unit configured to switch a storage capacitance for accumulating the charge converted by the conversion unit to the pixel signal.
However, Mabuchi discloses wherein the pixel further includes a switching unit configured to switch a storage capacitance for accumulating the charge converted by the conversion unit to the pixel signal (Figs. 1-3, [0045],[0050]and [0057]-[0065]: pixel 10 further includes a capacitor C and a switch transistor 25 between the floating diffusion FD and the reset transistor 22).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate wherein the pixel further includes a switching unit configured to switch a storage capacitance for accumulating the charge converted by the conversion unit to the pixel signal as taught by Mabuchi into Taura’s pixel. The suggestion/ motivation for doing so would be to achieve a high gain operation mode, a low gain operation mode, and a dynamic range expansion mode as the operation mode of the solid-state imaging device (Mabuchi: [0065]).
Regarding claim 3, Taura teaches the imaging element according to claim 1, except further comprising: a driving unit configured to set conversion efficiency in the transfer transistor to a high conversion rate and perform reading-out of the pixel signal by switching the storage capacitance to a large capacitance by the switching unit, and set the conversion efficiency in the transfer transistor to a low conversion rate and perform reading-out of the pixel signal by switching the storage capacitance to a small capacitance by the switching unit.
However, Mabuchi discloses further comprising: a driving unit (Fig. 1, vertical driving circuit 120 is configured to drive the pixels of the pixel unit 110) configured to set conversion efficiency in the transfer transistor to a high conversion rate and perform reading-out of the pixel signal by switching the storage capacitance to a large capacitance by the switching unit (Fig. 3, [0062] &[0066]: (2) When the switch pulse ØSw maintains a turned-on state, since the floating diffusion FD is connected to the capacitor C, the floating diffusion FD has a large capacity. Since the floating diffusion FD has a large capacity, a low gain is achieved instead of accepting many electrons, resulting in a reduction of sensitivity), and set the conversion efficiency in the transfer transistor to a low conversion rate and perform reading-out of the pixel signal by switching the storage capacitance to a small capacitance by the switching unit (Fig. 3, [0061]&[0066]: (1) When the switch pulse ØSw is turned off from an on state, since the floating diffusion FD is separated from the capacitor C, the floating diffusion FD has a small capacity. Since the floating diffusion FD has a small capacity, the potential of the floating diffusion FD is significantly reduced with a small number of electrons, resulting in the achievement of a high gain. From this standpoint, a signal with high sensitivity is output).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate a driving unit configured to set conversion efficiency in the transfer transistor to a high conversion rate and perform reading-out of the pixel signal by switching the storage capacitance to a large capacitance by the switching unit, and set the conversion efficiency in the transfer transistor to a low conversion rate and perform reading-out of the pixel signal by switching the storage capacitance to a small capacitance by the switching unit as taught by Mabuchi into Taura’s pixel. The suggestion/ motivation for doing so would be to achieve a high gain operation mode, a low gain operation mode, and a dynamic range expansion mode as the operation mode of the solid-state imaging device (Mabuchi: [0065]).
Regarding claim 9, Method claim 9 is drawn to the method of using the corresponding apparatus claimed in claims 1-3 combination. Therefore, method claim 9 corresponds to apparatus claims 1-3 and is rejected for the same reasons of obviousness as used above.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Taura (US 2010/0225776 A1, hereafter “Taura”), in view of Kono et al. (US 2011/0080493 A1, hereafter “Kono”).
Regarding claim 5, Taura teaches the imaging element according to claim 1, except wherein the connection wiring is laid out by avoiding overlap with a gate electrode of a transistor provided in the pixel in a plan view.
However, Kono discloses wherein the connection wiring is laid out by avoiding overlap with a gate electrode of a transistor provided in the pixel in a plan view (Figs. 2 and 4-8, [0027], [0032]&[0041]: conversion region 103 including an electrically conductive member. The electrically conductive member includes an electrically conductive member pattern (does not overlap with transistors in the pixel plan layout as illustrated in Fig. 2) formed in a wiring layer, and a plug (contact plug or via plug) which connects the diffusion region and amplification transistor 105).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate wherein the connection wiring is laid out by avoiding overlap with a gate electrode of a transistor provided in the pixel in a plan view as taught by Kono into Taura’s pixel. The suggestion/ motivation for doing so would be to provide an arrangement advantageous for reducing crosstalk (Kono: [0007]).
Claims 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over Taura (US 2010/0225776 A1, hereafter “Taura”), in view of Hashimoto et al. (US 2013/0229543 A1, hereafter “Hashimoto”).
Regarding claim 7, Taura teaches the imaging element according to claim 1, except wherein the pixel includes a plurality of photoelectric conversion portions having sensitivities different from each other.
However, Hashimoto discloses wherein the pixel includes a plurality of photoelectric conversion portions having sensitivities different from each other (Fig. 10, [0099]: pixel unit 100 which is configured of multiple photodiodes 1 and 51, where the surface area of the photodiode 1 is larger than the surface area of the photodiode 51. In other words, the sensitivity of the photodiode 1 is higher than the sensitivity of the photodiode 51).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate wherein the pixel includes a plurality of photoelectric conversion portions having sensitivities different from each other as taught by Hashimoto into Taura’s pixel. The suggestion/ motivation for doing so would be to allow Dynamic range to be expanded (Hashimoto: [0100]).
Regarding claim 8, the Taura and Hashimoto combination teaches the imaging element according to claim 7, in addition Hashimoto discloses further comprising: a driving unit (Fig. 10, [0042]: a vertical scanning circuit 2) configured to sequentially transfer pixel signals corresponding to charges generated in the plurality of respective photoelectric conversion portions to the diffusion layer and perform reading-out of the pixel signals (Fig. 12, [0057], [0062] &[0099]: At point-in-time t56, the transfer pulse ØT1 changes to H level. As a result, the signal charge generated by photoelectric conversion at the photodiode 1 is transferred to the input node of the amplifier MOS transistor 5. Next, at the point-in-time t65, the transfer pulse ØT2 changes to H level. As a result, the signal charge generated by photoelectric conversion at the photodiode 51 is transferred to the input node of the amplifier MOS transistor 5. The signal charge from the photodiode 1 is already being held at the input node of the amplifier MOS transistor 5. Therefore, by setting the transfer pulse ØT2 to H level, the signal charge from both the photodiodes 1 and 51 are held in an FD area. The signal based on the potential of the input node of the amplifier MOS transistor 5 to which the signal charge from both of these photodiodes 1 and 51 has been transferred, that is to say, the signal A+B, is output to the vertical signal line 7).
Contact
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ABDELAAZIZ TISSIRE whose telephone number is (571)270-7204. The examiner can normally be reached on Monday through Friday from 8 AM to 5 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ye Lin can be reached on 571-272-7372. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ABDELAAZIZ TISSIRE/Primary Examiner, Art Unit 2638
Prosecution Insights