DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Election/Restrictions
Claims 6-15 and 18-22 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 04 November 2025.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 4-5, 17, and 23 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tanaka (US 2023 / 0034225).
(It should be noted that the Tanaka reference was submitted by the applicant via Information Disclosure Statement on 11 February 2025.)
As pertaining to Claim 1, Tanaka discloses (see Fig. 1, Fig. 15, Fig. 17, and Fig. 18) a display device comprising:
a display panel (see (10) in Fig. 1) including a display area (11) in which pixel circuits (Pix) are disposed and a non-display area (i.e., a peripheral area outside of (11)) near the display area (11; see Page 4, Para. [0069]; and Page 5, Para. [0074]); and
a gate driver (see (40) in Fig. 1 corresponding to (410) in Fig. 15 and (420) in Fig. 18) configured to apply a scan signal (G), an emission signal (EA), and an inverted emission signal (EB) to the pixel circuit (Pix),
wherein the gate driver (40) includes:
at least one scan driver (see any portion of (410)) configured to output the scan signal (G);
a light emitting driver (see any portion of (420)) configured to output the emission signal (EA); and
inverting drivers (see the inverters at (40) in Fig. 18 and (M3) in Fig. 17) of which at least some output the inverted emission signal (EB) of which phase is inverted from that of the emission signal (EA) based on the scan signal (G) output from the at least one scan driver (again, see any portion of (410)) and the emission signal (EA) output from the light emitting driver (again, see any portion of (420)), wherein
the pixel circuit (Pix) further includes:
a light emitting element (OL);
a driving transistor (M1) having a first electrode (i.e., an upper electrode), a second electrode (i.e., a lower electrode), and a gate electrode (see (Vg)), the second electrode (i.e., a lower electrode) connected to the light emitting element (OD), the driving transistor (M1) configured to receive a high potential driving voltage (ELVDD) through the first electrode (i.e., the upper electrode), and configured to control an amount of driving current supplied to the light emitting element (OL) in response to a voltage of a gate electrode (Vg); and
a coupling capacitor (Cst) connected (i.e., via path (M7, M6, M1, M5)) between an inverted emission line (see (EB)) to which the inverted emission signal (EB) is applied and the gate electrode (see (Vg)) of the driving transistor (M1; see Page 11 through Page 12, Para. [0126]-[0129]; and Page 10 through Page 11, Para. [0120]).
As pertaining to Claim 2, Tanaka discloses (see Fig. 17) that the pixel circuit (Pix) further includes:
the light emitting element (OL) having an anode;
a first switching transistor (M2) transmitting a data voltage (D) to the gate electrode of the driving transistor (M1) in response to a first scan signal (G);
a light emitting transistor (M6) forming a current path between the driving transistor (M1) and the light emitting element (OL) in response to the emission signal (EA); and
an initialization transistor (M7) transmitting an initialization voltage (Vini) to the anode of the light emitting element (OL) in response to the inverted emission signal (EB; again, see Page 11 through Page 12, Para. [0126]-[0129]).
As pertaining to Claim 4, Tanaka discloses (see Fig. 1, Fig. 15, Fig. 17, and Fig. 18) that the scan driver (see any portion of (410)) includes:
a first scan driver (i.e., a first portion of (410)) configured to output the first scan signal (i.e., any (Gi) signal); and
a second scan driver (i.e., any other portion of (410)) configured to output a second scan signal (i.e., any other (Gi) signal), and
wherein the second scan signal (i.e., any other (Gi) signal) is applied to the inverting driver (i.e., see (M3) in Fig. 17; and see Page 4, Para. [0070]; Page 10 through Page 11, Para. [0120], and Page 12, Para. [0127]).
As pertaining to Claim 5, Tanaka discloses (see Fig. 1 and Fig. 18) that the inverting driver (see the inverters at (40) in Fig. 18 and (M3) in Fig. 17) is disposed closer to the display area (11) than the light emitting driver (see any portion of (420)) and the at least one scan driver (see any portion of (410)) are (see Fig. 1 in combination with Fig. 18, and note that the inverters at (40) are closer to display area (11) than (410) and (420); again, see Page 11 through Page 12, Para. [0126]-[0129]).
As pertaining to Claim 17, Tanaka discloses (see Fig. 17) that the coupling capacitor (Cst) transmits a coupling voltage (i.e., an arbitrary voltage) corresponding to the inverted emission signal (EB) to the gate electrode (see (Vg)) of the driving transistor (M1; see Page 12, Para. [0127]-[0129]).
As pertaining to Claim 23, Tanaka discloses (see Fig. 17) that the voltage at the gate electrode (see (Vg)) of the driving transistor (M1) is decreased by a selected level (i.e., any arbitrary level) due to a coupling voltage corresponding to the inverted emission signal (EB) in the coupling capacitor (Cst; again, see Page 12, Para. [0127]-[0129] and Page 2, Para. [0021]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Tanaka in view of Qian et al. (hereinafter “Qian” US 10,636,356).
As pertaining to Claim 3, Tanaka does not explicitly show that the gate driver is disposed at each of left and right sides of the display area in the non-display area and configured symmetrically. However, this configuration of the gate driver is well-known in the art.
In fact, in the same field of endeavor, Qian discloses (see Fig. 2 and Fig. 4) a display device comprising a gate driver (20B) configured to apply a scan signals and emission signals, wherein the gate driver (20B) is disposed at each of left and right sides of a display area (28) in a non-display area and configured symmetrically (see Col. 4, Ln. 31-55 and Col. 7, Ln. 18-41). It is a goal of Qian to provide an improved gate driver that allows for increased arrangement flexibility with reduced occupied space in the inactive area of the display device (see Col. 1, Ln. 20-24 and Ln. 52-64).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Tanaka with the teachings of Qian, such that the gate driver of Tanaka is disposed at each of left and right sides of the display area in the non-display area and configured symmetrically, as suggested by Qian, in order to provide an improved gate driver that allows for increased arrangement flexibility with reduced occupied space in the inactive area of the display device.
Response to Arguments
Applicant's arguments filed 25 February 2026 have been fully considered but they are not persuasive. The applicant has argued that none of the references relied upon by the examiner in the prior Office Action, particularly Tanaka, teach or fairly suggest the claimed “driving transistor configured to receive a high potential driving voltage through the first electrode, and configured to control an amount of driving current supplied to the light emitting element in response to a voltage of the gate electrode; and a coupling capacitor connected between an inverted emission line to which the inverted emission signal is applied and the gate electrode of the driving transistor" as recited in independent Claim 1 (see Remarks at Pages 8 and 9). The examiner respectfully disagrees as these feature are explicitly disclosed by Tanaka at least at Figure 17.
The applicant is respectfully reminded that the claimed invention must be interpreted in view of the originally filed disclosure. The originally filed Specification provides the definition for the term “connected to” at Paragraph [0020]:
“[0020] When a first component is "connected to" or "coupled to" a second component, it includes both a case in which the first component is directly connected or coupled to the second component or a case in which other components are interposed therebetween. On the other hand, when the first component is "directly connected to" or "directly coupled to" the second component, it means that other components are not interposed therebetween….”
Thus, as interpreted according to the originally filed disclosure, Tanaka provides for the claimed light emitting element (OL); the claimed driving transistor (M1); and the claimed coupling capacitor (Cst) connected (i.e., via path (M7, M6, M1, M5)) between an inverted emission line (see (EB)) to which the inverted emission signal (EB) is applied and the gate electrode (see (Vg)) of the driving transistor (M1).
Therefore, the rejection of Claims 1-5, 17, and 23 is maintained.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Chung (US 2008 / 0150846), corresponding to Chung (US 8,237,637), discloses (see Fig. 5 and Fig. 6) a gate driver configured to apply scan signals (S), emission signals (EM), and inverted emission signals (EMB).
Kim et al. (US 12,512,057), commonly assigned with the instant application, discloses (see Fig. 5) a pixel circuit similar to that disclosed by the instant application.
Ka et al. (US 11,996,051) discloses (see Fig. 4) a pixel circuit comprising a coupling capacitor (Nbst) connected between an emission line (GC) and a gate electrode of a driving transistor (TP1).
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JASON M MANDEVILLE whose telephone number is (571)270-3136. The examiner can normally be reached Mon - Fri 7:30AM-4:00PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chanh Nguyen can be reached at 571-272-7772. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/JASON M MANDEVILLE/Primary Examiner, Art Unit 2623
Prosecution Insights