The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claims 1-20 are presented for examination
Allowable Subject Matter
Claim 9-11 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant’s arguments, see pages 9-12, filed April 28, 2026, with respect to the rejection(s) of claim(s) 1 and 18 under U.S.C. 102 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn for claims 1 and 18. However, upon further consideration, a new ground(s) of rejection is made in view of previously cited prior art. The rejection of claim 13 is still maintained because applicant argued the reference does not teach the voltage provides to the partitions are not concurrent. That is not the case, because in paragraph 0017, it shows that, in some embodiments, fabric 115 can have a single stutter region while in other embodiments, fabric 115 can have multiple different stutter regions which wake up at different intervals. Portions of the fabric that need to wake up on similar intervals can be grouped together into a single stutter region. Other portions of the fabric that process unpredictable and/or non-periodic clients can be grouped together into the other region(s) which will remain power-gated while the stutter regions wake up on their different intervals. In this case, voltages supply to them as a group as well as individual. As well paragraph 0029, where multiple components can be controlled as group as well as independent that an enter or exit power gating which means voltage supply to them are controlled either as a group or invidiously.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
((a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-8 and 12-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hayashi (US Patent Application 20070176625).
As per claim 1, Hayashi teaches a system [100, fig. 2] comprising:
a digital logic circuit [10, fig. 1 or the enclosed dashed in figure 2] organized into multiple partitions [102A to 102H, fig. 2], the digital logic circuit including power gating logic [140, fig. 2] having one or more transistors [transistor switching: 0039] that are controllable to disable and enable power gating to the multiple partitions [0039-0041, 0044, as pointed out and shown in figure 2, master gate 140 is used with gate control 150 in order to power gating or simply enable and disable specific circuit block 102. For example, selectively supply operating power VDC1 the circuit blocks 102 in response to one or more respective control signals 154 output from the control circuit 152].
a power gating circuit [150 with 152, fig. 2] to independently control power supplied to the multiple partitions of the digital logic circuit [0035, as pointed out, the gate circuits 150 are each preferably operable to selectively supply operating power VDC1 the circuit blocks 102 in response to one or more respective control signals 154 output from the control circuit 152], and
to initiate a power state transition for the digital logic circuit to a power state in which the digital logic circuit is powered off except for the power gating logic [0035, as pointed out control signal from control circuit 152 is sent to circuit 150 to selectively power specific circuit 102, where the master circuit provide power to the gate circuit. In this case, the master circuit and the gate circuit can be considered always on circuit where either always need power, where circuit 102 does not need power all the times].
As per claim 13, Hayashi teaches a device [100, fig. 2] comprising:
a digital logic circuit [10, fig. 1 or the enclosed dashed in figure 2] organized into multiple partitions [102A to 102H, fig. 2].
a power gating circuit [150 with 152, fig. 2] to independently control amounts of voltage supplied to the multiple partitions of the digital logic circuit [0035, as pointed out, it is understood that each gate circuit 150 may selectively supply the operating power VDC1 to a single circuit block 102 (as shown) or to multiple blocks 102], the voltage concurrently supplied to two or more partitions of the multiple partitions being different [0035, as pointed out voltage can be supplied to a single circuit 102 block or multiple of them].
As per claim 18, Hayashi teaches a method [method shown in figure 3] comprising:
receiving, by a power gating circuit, a request to power on a partition of a digital logic circuit [0034-0035, power specific circuit block via control signal. For example, the gate circuits 150 are each preferably operable to selectively supply operating power VDC1 the circuit blocks 102 in response to one or more respective control signals 154 output from the control circuit 152. It is understood that each gate circuit 150 may selectively supply the operating power VDC1 to a single circuit block 102 (as shown) or to multiple blocks 10. The control signal can be based on requesting data and so forth].
issuing, by the power gating circuit, one or more control signals to power on the partition, the one or more control signals having programmed thereon a power up sequence for the partition through of electrical current and delays for transitioning between the different values of the electrical current [0038, 0042, control signal power up sequence is implemented to power up specific circuit blocks 102 in sequence. Where specific circuit 102 is powered by controlling a delay as shown in step 206 of figure 3].
As per claim 2, Hayashi teaches wherein the multiple partitions each include one or more circuitry partitions, subsystems having the power gating logic that is controllable to power on or off the one or more circuitry subsystems [0032, as shown in figure 2, each partition such as 102A having power gating circuit 150A, circuit 102E having power gating circuit 150E].
As per claim 3, Hayashi teaches wherein to independently control the power supplied to the multiple partitions, the power gating circuit is configured to issue one or more control signals to the power gating logic of one or more partitions, the one or more control signals causing the one or more circuitry subsystems of the one or more partitions to power on or off [0043, as pointed out, the gate circuit 150 is preferably operable to produce the operating power VDC1 on the respective power terminals 110 of the circuit blocks 102 by gating the power VDC1 on terminal 112 in accordance with the control signals 154].
As per claim 4, Hayashi teaches wherein the one or more control signals to power on the one or more partitions specify a power up sequence for the one or more partitions through different values of electrical current and delays for transitioning between the different values of the electrical current [0038, 0042, control signal power up sequence is implemented to power up specific circuit blocks 102 in sequence. Where specific circuit 102 is powered by controlling a delay as shown in step 206 of figure 3].
As per claim 5, Hayashi teaches wherein the one or more control signals are delivered to the power gating logic of multiple circuitry subsystems of the one or more partitions via repeater circuits which cause arrival of the one or more control signals at the power gating logic of the multiple circuitry subsystems concurrently [0052, from figures 2 and 4, control circuit that produce the control signals includes circuits that drive the control signals].
As per claim 6, Hayashi teaches wherein the power gating circuit includes multiple finite state machines assigned to corresponding partitions of the multiple partitions, and the power gating circuit is configured to [0044, circuit 150 includes logic gate circuits]:
receive a request to power on an individual partition of the multiple partitions [0044, specific circuit can be enabled and disabled based on the control signals];
issue, by a finite state machine assigned to the individual partition, the one or more control signals to the power gating logic of the individual partition in response to receipt of the request [0044, specific circuits can be enabled and disabled based on the control signals].
As per claim 7, Hayashi teaches the multiple partitions include at least one partition assigned to executing processes of the digital logic circuit, and at least one finite state machine assigned to the at least one partition is powered off when the at least one partition is powered off [0035, as shown in figure 2, voltage is provided to gage 150A where gage 150A provide power to circuit 102A, where the master circuit is provided VDC1 to the gate circuit].
As per claim 8, Hayashi teaches wherein to independently control the power supplied to the multiple partitions, the power gating circuit is configured to independently control amounts of voltage supplied to the multiple partitions of the digital logic circuit, the amounts of voltage concurrently supplied to at least two partitions of the multiple partitions being different [0035, as pointed out, each gate circuit 150 may selectively supply the operating power VDC1 to a single circuit block 102 (as shown) or to multiple blocks 102].
As per claim 12, Hayashi teaches the power gating circuit is clock gated when the digital logic circuit is in the power state [0044, clock gating circuit to enable and disable clock signal].
As per claim 14, Hayashi teaches the voltage supplied to an individual partition of the multiple partitions is different at different times [0038, as shown in figure 3 step 206, power delivered to the gate can be delayed].
As per claims 15-17 and 19-20, they do not teach or further define over the limitations recited in the rejected claims above. Therefore, claims 15-17 and 19-20 are also anticipated by Hayashi for the same reasons set forth in the rejected claims above.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VOLVICK DEROSE whose telephone number is (571)272-6260. The examiner can normally be reached on Monday-Friday 9AM-6PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jaweed Abbaszadeh can be reached on 571.270.1640. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/VOLVICK DEROSE/Primary Examiner, Art Unit 2176
Prosecution Insights