The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claims 1-20 are presented for examination
Allowable Subject Matter
Claim 5 and 9-11 is objected to as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3, 8, 12-15, and 17-18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Patel (US Patent Application 20240427395).
As per claim 1, Patel teaches a system [100, fig. 1] comprising:
a digital logic circuit [110, fig. 1] organized into multiple partitions [113, 115, fig. 1], the digital logic circuit including power gating logic [112, fig. 1] having one or more transistors [204, fig. 2] that are controllable to disable and enable power gating to the multiple partitions [0014, 0020, 0027 as shown in figures 1-2, computing device 100 include circuit block 110 that has partitions 113 and 115, where power manager 110 includes trigger logic 204 that can turn on and off power to specific partition. For example, the local power manager 200 takes an event signal 202 as input and generates one or more trigger signals 206 using the trigger logic 204. An event signal can include one or more input signals that can be logically combined to trigger power state transitions].
a power gating circuit [212, fig. 2] to:
independently control power supplied to the multiple partitions of the digital logic circuit [0021, as pointed out each device such as device 113 and device 115 can be controlled independently by the local power manager. For example, the computing device 100 includes multiple LPMs that each control one or more devices independently].
initiate a power state transition for the digital logic circuit to a power state in which each of the multiple partitions is powered off except for the power gating logic [0022, as pointed out the local power manager can control power to the device by initiate power state transition. For example, each power state table stores possible power state transitions for a respective device. Each power state transition changes the power state from an initial state to the next state. For example, local power manager 112 can store power state table A1 (114) and power state table A2 (116). Power state table A1 stores multiple power state transitions for device A1. Power state table A2 stores multiple power state transitions for device A2].
initiate a further power state transition out of the power state to power on at least one partition of the multiple partitions [0022, 0027, as pointed out the sequencer can initiate one power state transition after the next one. For instance, a device can be powered on as well as power off. As an example, an event signal that includes a logic value can be in an ON state or an OFF state. In some implementations, each event signal can be enabled or disabled via Control and Status Register (CSR). In some implementations, an event signal can be assumed to be Active High when the event signal is generic, and if the event signal received by the LPM is Active Low, it can be inverted to Active High via the CSR].
As per claim 13, Patel teaches a device comprising [100, fig. 1]:
a digital logic circuit [110, fig. 1] organized into multiple partitions [113, 115, fig. 1].
a power gating circuit [112, fig. 1] to independently control amounts of voltage supplied to the multiple partitions of the digital logic circuit by concurrently supplying a first amount of voltage to a first powered on partition of the multiple partitions and a second amount of voltage to a second powered on partition of the multiple partitions [0003, 0032, as pointed out different power gating based on the voltage level such as idle state of a CPU as well as normal state of that CPU. For example, when a CPU is in an idle state, the system can change the power state of the CPU to a low power state (e.g., switching to a lower voltage) in order to reduce the power consumption. Power management can include turning on/off the power, controlling voltage or frequency, switching to a low-power state when inactive, and so on].
As per claim 2, Patel teaches multiple partitions each include one or more circuitry subsystems having the power gating logic that is controllable to power on or off the one or more circuitry subsystems [0022, 0027, as shown in figure 1, for example device 123 can be controlled by local power manager 122].
As per claim 3, Patel teaches to independently control the power supplied to the multiple partitions, the power gating circuit is configured to issue one or more control signals to the power gating logic of one or more partitions, the one or more control signals causing the one or more circuitry subsystems of the one or more partitions to power on or off [0026, sequencer 204 receives event signals to enable power state transition. For example, the one or more power sequencers 212 are configured to execute respective instruction sequences when a power state transition is triggered by the trigger signal 206].
As per claim 5, Patel teaches the one or more control signals are delivered to the power gating logic of multiple circuitry subsystems of the one or more partitions via repeater circuits which cause arrival of the one or more control signals at the power gating logic of the multiple circuitry subsystems concurrently.
As per claim 8, Patel concurrently supply a first amount of voltage to a first powered on partition of the multiple partitions and a second amount of voltage to a second powered on partition of the multiple partitions [0003, 0032, as pointed out different power gating based on the voltage level such as idle state of a CPU as well as normal state of that CPU. For example, when a CPU is in an idle state, the system can change the power state of the CPU to a low power state (e.g., switching to a lower voltage) in order to reduce the power consumption. Power management can include turning on/off the power, controlling voltage or frequency, switching to a low-power state when inactive, and so on].
As per claim 12, Patel teaches the power gating circuit is clock gated when the digital logic circuit is in the power state [0051, clock instruction power gating].
As per claims 14-15 and 17, they do not teach or further define over the limitations recited in the rejected claims above. Therefore, claims 14-15 and 17 are also anticipated by Bircher for the same reasons set forth in the rejected claims above.
Claim 18 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Takayanagi (US Patent Application 20130111254).
As per claim 18, Takayanagi teaches a method [600, fig. 6] comprising:
receiving, by a power gating circuit, a request to power on a partition of a digital logic circuit [90, as pointed out request to power on specific functional block of the circuit can be received. For example, power manager 18 may be configured to process power on request for each of the power gated functional block of integrated circuit 30. In this example, four request lines, Req0, Req1, Req2, and Req3 are shown being provided to power manager 18 from an external source].
issuing, by the power gating circuit, one or more control signals to power on the partition, the one or more control signals having programmed thereon a power up sequence for the partition through different values of electrical current and delays for transitioning between the different values of the electrical current [0088-0092, as pointed out different request lines are used for different functional block where each draw specific current and each can be power up based on current draw and time as shown in figure 12. Different functional blocks are powered up at different time. For example, three power on requests have been simultaneously received and arbitrated. The results of the arbitration have determined that processor core 31A is to be powered up first, followed by processor core 31B, and finally graphics unit 35. Power is first applied to processor core 31A by asserting the corresponding enable signal and activating power switches therein. As well as FIG. 12B graphically illustrates a difference between fast and slow cases for two functional blocks. In the fast case, the total current peaks are greater than those in the slow cases. Furthermore, the slope representing di/dt is greater for the fast case than the slow case. Since the current peaks are reached faster during the fast case, power gated functional blocks are powered on faster].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4, 6-7, 16 and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Patel (US Patent Application 20240427395) in the view of Takayanagi (US Patent Application 20130111254).
As per claim 4, Patel does not teach one or more control signals to power on the one or more partitions specify a power up sequence for the one or more partitions through different values of electrical current and delays for transitioning between the different values of electrical current.
However, Takayanagi teaches one or more control signals to power on the one or more partitions specify a power up sequence for the one or more partitions through different values of electrical current and delays for transitioning between the different values of electrical current [0088-0092, as pointed out different request lines are used for different functional block where each draw specific current and each can be power up based on current draw and time as shown in figure 12. Different functional blocks are powered up at different time. For example, three power on requests have been simultaneously received and arbitrated. The results of the arbitration have determined that processor core 31A is to be powered up first, followed by processor core 31B, and finally graphics unit 35. Power is first applied to processor core 31A by asserting the corresponding enable signal and activating power switches therein. As well as FIG. 12B graphically illustrates a difference between fast and slow cases for two functional blocks. In the fast case, the total current peaks are greater than those in the slow cases. Furthermore, the slope representing di/dt is greater for the fast case than the slow case. Since the current peaks are reached faster during the fast case, power gated functional blocks are powered on faster].
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the design of Patel to include the method of Takayanagi to measure current and add transition delays to the devices.
As per claim 6, Patel does not teach the power gating circuit includes multiple finite state machines assigned to corresponding partitions of the multiple partitions, and the power gating circuit is configured to: receive a request to power on an individual partition of the multiple partitions; and issue, by a finite state machine assigned to the individual partition, the one or more control signals to the power gating logic of the individual partition in response to receipt of the request.
However, Takayanagi teaches the power gating circuit includes multiple finite state machines assigned to corresponding partitions of the multiple partitions, and the power gating circuit is configured to [0041, state transition logic]:
receive a request to power on an individual partition of the multiple partitions [90, as pointed out request to power on specific functional block of the circuit can be received. For example, power manager 18 may be configured to process power on request for each of the power gated functional block of integrated circuit 30. In this example, four request lines, Req0, Req1, Req2, and Req3 are shown being provided to power manager 18 from an external source].
issue, by a finite state machine assigned to the individual partition, the one or more control signals to the power gating logic of the individual partition in response to receipt of the request [0088-0092, multiple partitions are transitioning based on the request].
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the design of Patel to include the method of Takayanagi to use control signal logic to transition functional block from one power state to another power state.
As per claim 7, Patel teaches multiple partitions include at least one partition assigned to executing processes of the digital logic circuit, and at least one finite state machine assigned to the at least one partition is powered off when the at least one partition is powered off.
However, Takayanagi teaches multiple partitions include at least one partition assigned to executing processes of the digital logic circuit, and at least one finite state machine assigned to the at least one partition is powered off when the at least one partition is powered off [0041, control power state transition from one level to another level].
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the design of Patel to include the method of Takayanagi to use control signal logic to transition functional block from one power state to another power state.
As per claims 16 and 19-20, they do not teach or further define over the limitations recited in the rejected claims above. Therefore, claims 16 and 19-20 are also rejected as being unpatentable over Patel in view of Takayanagi for the same reasons set forth in the rejected claims above.
Conclusion
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/VOLVICK DEROSE/Primary Examiner, Art Unit 2176
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