Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Response to Amendment
The amendment filed on November 24, 2025 has been received and entered.
Applicant’s Amendments to the Claims have been received and acknowledged.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 11/24/2025 is being considered by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1 and 3-11 are rejected under 35 U.S.C. 103 as being unpatentable over Ware et al. (U.S. Publication No. 2017/0133070 A1), hereafter referred to as Ware’070 in view of Takaku et al. (U.S. Publication No. 2008/0046631 A1), hereafter referred to as Takaku’631.
Referring to claim 1, Ware’070 as claimed, a memory device (see Fig. 3C) comprising: a memory cell array configured to store data (memory devices 374a-b, see Fig. 3C); plurality of data lines configured to transmit the data (various paths to memories represented by lines and arrows, see Figs. 1A-B, 3A, 5A); path changing switches connected to the plurality of data lines (components such as multiplexers (MUX) to selectively route data/commands, see paras. [0053], [0078], [0092], [0112], [0127], Figs. 1A, 3C, 5C, 8A, 8D); and a controller configured to receive a first selection signal and a second selection signal, which are rank selecting signals from a memory controller (one or more chip select or rank enable signals can be used to effect or assist with rank selection, see paras. [0082], [0089], [0095], [0105]; memory controller, see Figs. 1A-B, 3C, 5A-C), wherein the controller is configured to control opening/closing of the path changing switches based on the first selection signal and the second selection signal (switching ranks and various memory configurations, see paras. [0071], [0078], [0079], [0090], [0095], and [0105]), wherein the controller is configured to generate a first signal for instructing a rank (number of banks, ranks of memory, see paras. [0078]), [0079], [0127]), and a second signal for instructing a size of input/output data (row width and row depth reconfigured to desired word size, size of various paths, see paras. [0078], [0112], and [0127]), and to generate control signals for controlling opening/closing of the path changing switches based on the first selection signal, the second selection signal, the first signal, and the second signal (switching ranks and various memory configurations, see paras. [0071], [0078], [0079], [0090], [0095], and [0105]).
However, Ware’070 does not explicitly teach opening/closing of path when a rank is a dual rank.
Takaku’631 discloses opening/closing of path when a rank is a dual rank (asserts the signals for the rank selection by employing CS0, CS1 as specified if taking the 2-rank memory architecture, wherein A14 is employed as the address signal link; in increasing the rank count, the control unit ON/OFF-controls the ODT at the predetermined rank in accordance with the rank count, whereby the rise in the number of stubs can be restrained, see paras. [0096], [0099]-[0105] and Figs 9, 10A-B).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Ware’070’s invention to comprise opening/closing of path when a rank is a dual rank, as taught by Takaku’631, in order to increase the number of ranks of the memory module with the small change in architecture (see para. [0038]).
As to claim 3, Ware’070 also discloses the controller is configured to generate the first signal to have a first-level (ranks or sub-ranks of memory, see paras. [0078]), [0079], [0084], [0127]) in order to configure the memory device with a dual rank (two ranks of memory, see paras. [0079], [0113] and Fig. 5C).
As to claim 4, Ware’070 also discloses the controller is configured to generate the second signal of a first-level in order to configure the memory device to inputs/output 8-bit data (the DQ path in the configuration of Fig. 3C is eight bits wide, see para. [0082] and Fig. 3C).
As to claim 5, Ware’070 also discloses the controller generates the first signal (number of banks, ranks of memory, see paras. [0078]), [0079], [0127]) based on the first selection signal and the second selection signal (one or more chip select or rank enable signals can be used to effect or assist with rank selection, see paras. [0082], [0089], [0095], [0105]; memory controller, see Figs. 1A-B, 3C, 5A-C).
As to claim 6, Ware’070 also discloses the controller generates the first signal and the second signal based on serial presence detect (SPD) information (individual DRAM memory devices coupled with memory controller having a shared DQ path, shared CA timing path, and a shared CA path. Each of these paths is a conductive path. The memory controller having a number of pins which respectively convey the DQ, timing, and CA signals to the aforementioned paths., see para. [0104]; also note: various configurations/signaling parameters and presence or respective mode registers in the memory devices used to configure the integrated circuit devices for operation, see paras. [0083], [0127] and [0128]).
As to claim 7, Ware’070 also discloses the plurality of data lines include first data lines and second data lines (various paths to memories represented by lines and arrows, see Figs. 1A-B. 3A), the controller generates a first control signal, a second control signal and a third control signal (effective switch in the DQ path (e.g., the command is a column access command directed to a new rank which will have the effect of driving data out only the shared DQ path), see para. [0072]; also note: multiplexers for the DQ paths configured dynamically to support the desired configuration (as defined by the mode register), with the number of banks, row width, and row depth being reconfigured to desired word size. For example, in a first mode in which all four DQ ports are used…In a second mode in which only DQ-A and DQ-C are active, and in which the multiplexers route memory array data only to these DQ ports, see paras. [0078], [0084]), and the path changing switches include: a first path changing switch connected to the first data lines and configured to be opened/closed based on the first control signal (components such as multiplexers (MUX) to selectively route data/commands, see paras. [0053], [0078], [0092], [0112], [0127], Figs. 1A, 3C, 5C, 8A, 8D); a second path changing switch connected to the second data lines and configured to be opened/closed based on the second control signal (components such as multiplexers (MUX) to selectively route data/commands, see paras. [0053], [0078], [0092], [0112], [0127], Figs. 1A, 3C, 5C, 8A, 8D); and a third path changing switch connected to the first data lines and the second data lines and configured to be opened/closed based on the third control signal (components such as multiplexers (MUX) to selectively route data/commands, see paras. [0053], [0078], [0092], [0112], [0127], Figs. 1A, 3C, 5C, 8A, 8D).
As to claim 8, Ware’070 also discloses the controller generates a first signal indicating whether the memory device has a dual rank configuration (two ranks of memory, see paras. [0079], [0113] and Fig. 5C) and a second signal indicating a size of input/output data (row width and row depth reconfigured to desired word size, size of various paths, see paras. [0078], [0112], and [0127]), and the first control signal, the second control signal, and the third control signal are generated by the controller based on the first selection signal, the second selection signal, the first signal, and the second signal (effective switch in the DQ path (e.g., the command is a column access command directed to a new rank which will have the effect of driving data out only the shared DQ path), see para. [0072]; also note: multiplexers for the DQ paths configured dynamically to support the desired configuration (as defined by the mode register), with the number of banks, row width, and row depth being reconfigured to desired word size. For example, in a first mode in which all four DQ ports are used…In a second mode in which only DQ-A and DQ-C are active, and in which the multiplexers route memory array data only to these DQ ports, see paras. [0078], [0084]; also note: one or more chip select or rank enable signals can be used to effect or assist with rank selection, see paras. [0082], [0089], [0095], [0105]; memory controller, see Figs. 1A-B, 3C, 5A-C and switching ranks and various memory configurations, see paras. [0071], [0078], [0079], [0090], [0095], and [0105]).
As to claim 9, Ware’070 also discloses the controller includes logic circuits configured to generate the first control signal, the second control signal, and the third control signal based on the first selection signal, the second selection signal, the first signal, and the second signal (logic circuits, see Figs. 1B, 3A, 3C, 4A-B, 5A, 5C and paras. [0069], [0083]).
As to claim 10, Ware’070 also discloses the logic circuits include an inverter, an AND gate, an OR gate, and an XOR gate (inverters, AND gate, and various logic components, see para. [0134], Figs. 1A-B, 3C, 5C, 7A-B, 8A, 9A-C).
As to claim 11, Ware’070 a first buffer connected to the first data lines and configured to be operated based on a fourth control signal (buffers and other resources used to transfer data between the array and IO circuitry, see paras. [0048] and on DQ lines in Figs. 1A-B, 3C, 5C, 6D, 7A-C); and a second buffer connected to the second data lines and configured to be operated based on a fifth control signal (buffers and other resources used to transfer data between the array and IO circuitry, see paras. [0048] and on DQ lines in Figs. 1A-B, 3C, 5C, 6D, 7A-C), wherein the controller further generates the fourth control signal and the fifth control signal based on the second selection signal, the first signal, and the second signal (effective switch in the DQ path (e.g., the command is a column access command directed to a new rank which will have the effect of driving data out only the shared DQ path), see para. [0072]; also note: multiplexers for the DQ paths configured dynamically to support the desired configuration (as defined by the mode register), with the number of banks, row width, and row depth being reconfigured to desired word size. For example, in a first mode in which all four DQ ports are used…In a second mode in which only DQ-A and DQ-C are active, and in which the multiplexers route memory array data only to these DQ ports, see paras. [0078], [0084]; also note: one or more chip select or rank enable signals can be used to effect or assist with rank selection, see paras. [0082], [0089], [0095], [0105]; memory controller, see Figs. 1A-B, 3C, 5A-C and switching ranks and various memory configurations, see paras. [0071], [0078], [0079], [0090], [0095], and [0105]).
Allowable Subject Matter
Claims 12-14 and 16-20 are allowed.
Response to Arguments
Applicant's arguments filed 11/24/2025 have been fully considered but they are moot due to new grounds of rejection.
In summary, Ware’070 and Takaku’631 teach the claimed limitations as set forth.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant’s
disclosure.
SONG et al. (U.S. Publication No. 2013/0069689 A1) discloses a method for operating memory device including receiving an on-die termination signal through an ODT pin and issuing command or controlling an ODT circuit accordingly.
Warnes et al. (U.S. Patent No. 8,539,145 B1) discloses increasing the number of ranks per channel.
Saito et al. (U.S. Publication No. 2010/0309706 A1) discloses load reduced memory module and memory system.
KIM et al. (U.S. Publication No. 2021/0174861 A1) discloses a method of controlling on-die termination during read/write operation on a target memory unit.
KWON et al. (U.S. Publication No. 2017/0168746 A1) discloses a semiconductor memory device having rank interleaving operation in memory module.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
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/TITUS WONG/Primary Examiner, Art Unit 2181
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