DETAILED ACTION
This action is responsive to the application filed 17 Jul 2024. Claims 1-18 are pending. Claims 1 and 10 are independent.
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Application Title
The Examiner proposes the below Application Title change in accordance with MPEP 606.01 and MPEP 1302.04(a) to improve the descriptive nature of the title. The Applicant can suggest an alternative title if desired. The Application Title should be changed to the following:
“MEMORY PROGRAMMING SCHEMES WITH ADJUSTABLE VERIFICATION VOLTAGES FOR REDUCING DATA RETENTION LOSS”
No action is required by the applicant. If an allowance is processed, the Examiner will change the name as part of the Examiner’s Amendment process.
Allowable Subject Matter
Claims 4 and 13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim Rejections – 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless —
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claims 1 – 3, 5, 7, 8, 10 – 12, 14, 16, and 17 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Lee, et al, U.S. Patent Application Publication 2024/0412793 (“Lee”).
Regarding claim 1, Lee teaches:
An apparatus for data storage, comprising: a plurality of memory cells coupled to multiple word lines (WLs), the memory cells configured to store data values in multiple respective predefined programming levels; and (Lee, fig 6, “[0041] The non-volatile memory 600 includes a memory cell array 610, a controller 620, and a sense amplifier 630. The memory cell array 610 may include a plurality of memory cell strings, and each memory cell string is coupled to a plurality of word lines.”; a NVM memory array with a controller, wordlines, and memory cells to store data. Note: “multiple respective programming levels” does not require more than two programming levels).
storage circuitry, configured to: receive data values for storage in the memory cells of a given WL; (Lee, fig 6, 4A, “[0018] In detail, a controller of the non-volatile memory may perform a reading operation on a plurality of memory cells on the Nth word line. A sense amplifier of the nonvolatile memory may compare current on bit lines of the memory cells on the Nth word line with a reference current to obtain a comparison result. [0034] Referring to FIG. 4A and FIG. 4B below, FIG. 4A and FIG. 4B are schematic diagrams showing the distribution state of the memory cells after the programming operation of the non-volatile memory”; an NVM storage device with the wordline, bitline, and controller circuitry to send data values and to store data in memory cells).
select memory cells of the given WL that are to store a given data value among the received data values; (Lee, fig 2, “[0024] Referring to FIG. 2 below, FIG. 2 is a flowchart showing a programming method of a non-volatile memory. In step S210, a programming operation for an N+1th word line WLn+1 is started.”; a selected memory cell on a selected N+1th wordline).
set a verification voltage for programming the selected memory cells, so that a difference between the verification voltage and a read voltage predetermined for the selected memory cells depends on a rate of drift that is expected to occur to a threshold voltage distribution (TVD) associated with the selected memory cells when programmed; (Lee, fig 2, “[0025] In step S230, a reading operation may be performed on the memory cells of an Nth word line WLn, so as to determine the equivalent threshold voltage of the memory cells of the Nth word line WLn. [0026] In step S240, whether the equivalent threshold voltage of the word line WLn is in a high threshold voltage state is determined. If the word line WLn is in a high threshold voltage state, step S252 is executed. On the contrary, if the word line WLn is in a low threshold voltage state, step S251 is executed. [0027] In step S251, the controller may maintain the values of the programming verification voltages E, F, and G unchanged. In step S252, the controller selects the programming verification voltages F and Gas the selected programming verification voltages.”; a unselected wordline WLn is tested to see if it has a high or low threshold voltage distribution; a verification voltage is selected for the selected N+1th wordline based on the neighboring cells value; the values F’ and G’ are based on measured results of a large population and are used as “expected values” based on the results of testing those data voltage values).
apply one or more programming pulses to the given WL; and verify that the selected memory cells have been programmed successfully using the set verification voltage. (Lee, fig 2, 3, “[0027] Then, the controller may perform a programming operation and a programing verification operation on the memory cell 350 according to the programming verification voltage E, perform a programming operation and a programing verification operation on the memory cell 360’ according to the adjusted programming verification voltage F’, and perform a programming operation and a programing verification operation on the memory cell 370’ according to the adjusted programming verification voltage G’.”; the selected wordline WLn+1 is programmed with the newly selected programming pulses and verification operations; that the programming operation is performed using either one set or the other of verification voltages).
Regarding claim 2, Lee teaches The apparatus according to claim 1, wherein the storage circuitry is configured to set the verification voltage based at least on the given data value. (Lee, fig 3, “Hereinafter, also referring to FIG. 3 which is a schematic diagram of a programming operation of a non-volatile memory according to an embodiment of the disclosure, in the programming operation of the N+1th word line WLn+1, a plurality of programming verification voltages A, B, C, D, E, F, and G respectively corresponding to a plurality of logic values are set, wherein the programming verification voltages satisfy A<B<C<D<E<F<G.”; the different verification voltages are initially set at A/B…r/G based on initial conditions and data stored; the verification voltages are either kept at F and G, or updated to F’ and G’ based on expectations and measured values of the data stored).
Regarding claim 3, Lee teaches:
The apparatus according to claim 2, wherein the storage circuitry is configured to receive neighbor data values for storage in neighbor memory cells in an adjacent WL, and (Lee, fig 2, 3, “[0025] In step S230, a reading operation may be performed on the memory cells of an Nth word line WLn, so as to determine the equivalent threshold voltage of the memory cells of the Nth word line WLn.”; that a neighbor wordline WLn is tested for its value).
to set the verification voltage for the selected memory cells whose neighbor memory cells are to be programmed to a given neighbor data value, based both on the given data value and on the given neighbor data value. (Lee, fig 2, 3, “[0026] In step S240, whether the equivalent threshold voltage of the word line WLn is in a high threshold voltage state is determined. If the word line WLn is in a high threshold voltage state, step S252 is executed. On the contrary, if the word line WLn is in a low threshold voltage state, step S251 is executed.”; a new verification voltage is selected for WLn+1 MC based on the data value stored in neighbor WLn, either high or low based on decision in step 240).
Regarding claim 5, Lee teaches The apparatus according to claim 3, wherein the storage circuitry is configured to read neighbor memory cells previously programmed in an adjacent WL using one or more read thresholds that divide a threshold voltage axis to two or more ranges, and to set the verification voltage based on the given data value and on the ranges to which the neighbor memory cells belong. (Lee, fig 2, “[0025] In step S230, a reading operation may be performed on the memory cells of an Nth word line WLn, so as to determine the equivalent threshold voltage of the memory cells of the Nth word line WLn. [0026] In step S240, whether the equivalent threshold voltage of the word line WLn is in a high threshold voltage state is determined. If the word line WLn is in a high threshold voltage state, step S252 is executed. On the contrary, if the word line WLn is in a low threshold voltage state, step S251 is executed. [0027] In step S251, the controller may maintain the values of the programming verification voltages E, F, and G unchanged. In step S252, the controller selects the programming verification voltages F and Gas the selected programming verification voltages.”; a unselected wordline WLn is tested to see if it has a high or low threshold voltage distribution; a verification voltage is selected for the selected N+1th wordline based on the neighboring cells value; the values F’ and G’ are based on measured results of a large population and are used as “expected values” based on the results of testing those data voltage values).
Regarding claim 7, Lee teaches The apparatus according to claim 1, wherein the storage circuitry is configured to verify that the selected memory cells have been programmed successfully by using the set verification voltage for reading the selected memory cells. (Lee, fig 1, “[0020] In step S120, when a programming operation is performed on a plurality of memory cells of an N +1th word line, whether to adjust at least one selected programming verification voltage of a plurality of programming verification voltages by an offset value may be decided according to the determination result generated in step S110. [0021] Then, the controller may perform a programming operation and a programming verification operation on the memory cells of the N+1th word line according to the adjusted programming verification voltage.”; when the verification voltages are determined (from the steps of figure 2), then the memory cells are programmed with those verification voltage levels).
Regarding claim 8, Lee teaches The apparatus according to claim 1, wherein the storage circuitry is configured to verify that the selected memory cells have been programmed successfully by sensing the selected memory cells for a sensing duration that depends on the verification voltage. (Lee, fig 1, “[0020] In step S120, when a programming operation is performed on a plurality of memory cells of an N +1th word line, whether to adjust at least one selected programming verification voltage of a plurality of programming verification voltages by an offset value may be decided according to the determination result generated in step S110. [0021] Then, the controller may perform a programming operation and a programming verification operation on the memory cells of the N+1th word line according to the adjusted programming verification voltage. [0029] Therefore, the programming verification operation for some of the memory cells in the word line WLn+1 is completed first in step S220, so as to release a sufficient size of the cache space for performing the reading operation of the equivalent threshold voltage of the memory cells of the word line WLn.”; when the verification voltages are determined (from the steps of figure 2), then the memory cells are programmed with those verification voltage levels; the verification of S220 indicates that the memory storage has been successful before proceeding to the next memory cells).
Regarding claim 10, Lee teaches:
A method for data storage, comprising: in a storage apparatus that comprises a plurality of memory cells coupled to multiple word lines (WLs), the memory cells store data values in multiple respective predefined programming levels, (Lee, fig 6, “[0041] The non-volatile memory 600 includes a memory cell array 610, a controller 620, and a sense amplifier 630. The memory cell array 610 may include a plurality of memory cell strings, and each memory cell string is coupled to a plurality of word lines.”; a NVM memory array with a controller, wordlines, and memory cells to store data. Note: “multiple respective programming levels” does not require more than two programming levels).
receiving data values for storage in the memory cells of a given WL; (Lee, fig 6, 4A, “[0018] In detail, a controller of the non-volatile memory may perform a reading operation on a plurality of memory cells on the Nth word line. A sense amplifier of the nonvolatile memory may compare current on bit lines of the memory cells on the Nth word line with a reference current to obtain a comparison result. [0034] Referring to FIG. 4A and FIG. 4B below, FIG. 4A and FIG. 4B are schematic diagrams showing the distribution state of the memory cells after the programming operation of the non-volatile memory”; an NVM storage device with the wordline, bitline, and controller circuitry to send data values and to store data in memory cells).
selecting memory cells of the given WL that are to store a given data value among the received data values; (Lee, fig 2, “[0024] Referring to FIG. 2 below, FIG. 2 is a flowchart showing a programming method of a non-volatile memory. In step S210, a programming operation for an N+1th word line WLn+1 is started.”; a selected memory cell on a selected N+1th wordline).
setting a verification voltage for programming the selected memory cells, so that a difference between the verification voltage and a read voltage predetermined for the selected memory cells depends on a rate of drift that is expected to occur to a threshold voltage distribution (TVD) associated with the selected memory cells when programmed; (Lee, fig 2, “[0025] In step S230, a reading operation may be performed on the memory cells of an Nth word line WLn, so as to determine the equivalent threshold voltage of the memory cells of the Nth word line WLn. [0026] In step S240, whether the equivalent threshold voltage of the word line WLn is in a high threshold voltage state is determined. If the word line WLn is in a high threshold voltage state, step S252 is executed. On the contrary, if the word line WLn is in a low threshold voltage state, step S251 is executed. [0027] In step S251, the controller may maintain the values of the programming verification voltages E, F, and G unchanged. In step S252, the controller selects the programming verification voltages F and Gas the selected programming verification voltages.”; a unselected wordline WLn is tested to see if it has a high or low threshold voltage distribution; a verification voltage is selected for the selected N+1th wordline based on the neighboring cells value; the values F’ and G’ are based on measured results of a large population and are used as “expected values” based on the results of testing those data voltage values).
applying one or more programming pulses to the given WL; and verifying that the selected memory cells have been programmed successfully using the set verification voltage. (Lee, fig 2, 3, “[0027] Then, the controller may perform a programming operation and a programing verification operation on the memory cell 350 according to the programming verification voltage E, perform a programming operation and a programing verification operation on the memory cell 360’ according to the adjusted programming verification voltage F’, and perform a programming operation and a programing verification operation on the memory cell 370’ according to the adjusted programming verification voltage G’.”; the selected wordline WLn+1 is programmed with the newly selected programming pulses and verification operations; that the programming operation is performed using either one set or the other of verification voltages).
Regarding claim 11, Lee teaches The method according to claim 10, wherein setting the verification voltage comprises setting the verification voltage based at least on the given data value. (Lee, fig 3, “Hereinafter, also referring to FIG. 3 which is a schematic diagram of a programming operation of a non-volatile memory according to an embodiment of the disclosure, in the programming operation of the N+1th word line WLn+1, a plurality of programming verification voltages A, B, C, D, E, F, and G respectively corresponding to a plurality of logic values are set, wherein the programming verification voltages satisfy A<B<C<D<E<F<G.”; the different verification voltages are initially set at A/B…r/G based on initial conditions and data stored; the verification voltages are either kept at F and G, or updated to F’ and G’ based on expectations and measured values of the data stored).
Regarding claim 12, Lee teaches:
The method according to claim 11, and comprising receiving neighbor data values for storage in neighbor memory cells in an adjacent WL, and (Lee, fig 2, 3, “[0025] In step S230, a reading operation may be performed on the memory cells of an Nth word line WLn, so as to determine the equivalent threshold voltage of the memory cells of the Nth word line WLn.”; that a neighbor wordline WLn is tested for its value).
setting the verification voltage for the selected memory cells whose neighbor memory cells are to be programmed to a given neighbor data value, based both on the given data value and on the given neighbor data value. (Lee, fig 2, 3, “[0026] In step S240, whether the equivalent threshold voltage of the word line WLn is in a high threshold voltage state is determined. If the word line WLn is in a high threshold voltage state, step S252 is executed. On the contrary, if the word line WLn is in a low threshold voltage state, step S251 is executed.”; a new verification voltage is selected for WLn+1 MC based on the data value stored in neighbor WLn, either high or low based on decision in step 240).
Regarding claim 14, Lee teaches The method according to claim 12, and comprising reading neighbor memory cells previously programmed in an adjacent WL using one or more read thresholds that divide a threshold voltage axis to two or more ranges, and setting the verification voltage based on the given data value and on the ranges to which the neighbor memory cells belong. (Lee, fig 2, “[0025] In step S230, a reading operation may be performed on the memory cells of an Nth word line WLn, so as to determine the equivalent threshold voltage of the memory cells of the Nth word line WLn. [0026] In step S240, whether the equivalent threshold voltage of the word line WLn is in a high threshold voltage state is determined. If the word line WLn is in a high threshold voltage state, step S252 is executed. On the contrary, if the word line WLn is in a low threshold voltage state, step S251 is executed. [0027] In step S251, the controller may maintain the values of the programming verification voltages E, F, and G unchanged. In step S252, the controller selects the programming verification voltages F and Gas the selected programming verification voltages.”; a unselected wordline WLn is tested to see if it has a high or low threshold voltage distribution; a verification voltage is selected for the selected N+1th wordline based on the neighboring cells value; the values F’ and G’ are based on measured results of a large population and are used as “expected values” based on the results of testing those data voltage values).
Regarding claim 16, Lee teaches The method according to claim 10, wherein verifying that the selected memory cells have been programmed successfully comprises verifying that the selected memory cells have been programmed successfully by using the set verification voltage for reading the selected memory cells. (Lee, fig 1, “[0020] In step S120, when a programming operation is performed on a plurality of memory cells of an N +1th word line, whether to adjust at least one selected programming verification voltage of a plurality of programming verification voltages by an offset value may be decided according to the determination result generated in step S110. [0021] Then, the controller may perform a programming operation and a programming verification operation on the memory cells of the N+1th word line according to the adjusted programming verification voltage.”; when the verification voltages are determined (from the steps of figure 2), then the memory cells are programmed with those verification voltage levels).
Regarding claim 17, Lee teaches The method according to claim 10, wherein verifying that the selected memory cells have been programmed successfully comprises sensing the selected memory cells for a sensing duration that depends on the verification voltage. (Lee, fig 1, “[0020] In step S120, when a programming operation is performed on a plurality of memory cells of an N +1th word line, whether to adjust at least one selected programming verification voltage of a plurality of programming verification voltages by an offset value may be decided according to the determination result generated in step S110. [0021] Then, the controller may perform a programming operation and a programming verification operation on the memory cells of the N+1th word line according to the adjusted programming verification voltage. [0029] Therefore, the programming verification operation for some of the memory cells in the word line WLn+1 is completed first in step S220, so as to release a sufficient size of the cache space for performing the reading operation of the equivalent threshold voltage of the memory cells of the word line WLn.”; when the verification voltages are determined (from the steps of figure 2), then the memory cells are programmed with those verification voltage levels; the verification of S220 indicates that the memory storage has been successful before proceeding to the next memory cells).
Claim Rejections – 35 USC § 103
The following is a quotation of 35 U.S.C. 103, which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claims 6, 9, 15, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Zhao, et al, U.S. Patent Application Publication 2023/0238067 (“Zhao”).
Regarding claim 6, Lee teaches the apparatus according to claim 1.
Lee does not explicitly teach wherein the storage circuity is configured to program the selected memory cells using a coarse programming phase and a fine programming phase, and to set the verification voltage for performing the fine programming phase..
Zhao teaches wherein the storage circuity is configured to program the selected memory cells using a coarse programming phase and a fine programming phase, and to set the verification voltage for performing the fine programming phase. (Zhao, fig 8A, “[0108] Next, in a next loop (e.g., a second loop, Loop 2), a program operation is performed in a program phase using a result of comparison during the first loop (e.g., Loop1), a first verify operation (e.g., a coarse verify operation) is performed in a first verify phase (e.g., a coarse verify phase) following the program phase, and a second verify operation (e.g., a fine verify operation) is performed in a second verify phase (e.g., a fine verify phase) following the first verify phase… In some implementations, the low verify level VL may be a coarse verify voltage (e.g., a first verify voltage applied during the first verify operation in the first verify phase), while the high verify level VH may be a fine verify voltage (e.g., a second verify voltage applied during the second verify operation in the second verify phase).”; that programming often uses multiple rates of programming with large jumps (coarse) and smaller voltage jumps (fine programming)).
In view of the teachings of Zhao it would have been obvious for a person of ordinary skill in the art to apply the teachings of Zhao to Lee before the effective filing date of the claimed invention in order to teach programming memory cells. The teachings of Zhao, in the same or in a similar field of endeavor with Lee, can combine Zhao’s explicit voltages used in ISPP and Lee’s less explicit programming operations. The two programming operations using slightly differing voltages for wordlines and bitlines perform the same functions as they perform separately and being no more “the combining of prior art elements according to known methods to yield predictable results” (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)).
Regarding claim 9, Lee teaches the storage system according to claim 1.
Lee does not explicitly teach wherein the storage circuitry is configured to verify that the selected memory cells have been programmed successfully by setting a predefined bias voltage to bit lines to which the selected memory cells are coupled, so that the bias voltage depends on the verification voltage..
Zhao teaches wherein the storage circuitry is configured to verify that the selected memory cells have been programmed successfully by setting a predefined bias voltage to bit lines to which the selected memory cells are coupled, so that the bias voltage depends on the verification voltage. (Zhao, fig 8A, “[0108] In some implementations, the low verify level VL may be a coarse verify voltage (e.g., a first verify voltage applied during the first verify operation in the first verify phase), while the high verify level VH may be a fine verify voltage (e.g., a second verify voltage applied during the second verify operation in the second verify phase). [0110] The method applies incremental-step-pulse programming (ISPP) with multiple bit line bias voltages (e.g., 3 bit line (3BL), 4 bit line (4BL), or more bit line bias voltages)… Step 804: Compare the threshold voltage Vt of the memory cell with the high verify level VH and/or the low verify level VL; if the threshold voltage Vt of the memory cell is higher than the high verify level VH, proceed to Step 806; if the threshold voltage Vt of the memory cell is higher than the low verify level VL but lower than the high verify level VH, proceed to Step 808; if the threshold voltage Vt of the memory cell is lower than the low verify level VL, proceed to Step 810: Step 806:”; that the VL (coarse programming) and VH (fine programming) can be coordinated with a bias voltage applied to the bit line to adjust the programming speed for a memory cell).
In view of the teachings of Zhao it would have been obvious for a person of ordinary skill in the art to apply the teachings of Zhao to Lee before the effective filing date of the claimed invention in order to teach programming memory cells. The teachings of Zhao, in the same or in a similar field of endeavor with Lee, can combine Zhao’s explicit voltages used in ISPP and Lee’s less explicit programming operations. The two programming operations using slightly differing voltages for wordlines and bitlines perform the same functions as they perform separately and being no more “the combining of prior art elements according to known methods to yield predictable results” (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)).
Regarding claim 15, Lee teaches the method according to claim 10.
Lee does not explicitly teach and comprising programming the selected memory cells using a coarse programming phase and a fine programming phase, and setting the verification voltage for performing the fine programming phase..
Zhao teaches and comprising programming the selected memory cells using a coarse programming phase and a fine programming phase, and setting the verification voltage for performing the fine programming phase. (Zhao, fig 8A, “[0108] Next, in a next loop (e.g., a second loop, Loop 2), a program operation is performed in a program phase using a result of comparison during the first loop (e.g., Loop1), a first verify operation (e.g., a coarse verify operation) is performed in a first verify phase (e.g., a coarse verify phase) following the program phase, and a second verify operation (e.g., a fine verify operation) is performed in a second verify phase (e.g., a fine verify phase) following the first verify phase… In some implementations, the low verify level VL may be a coarse verify voltage (e.g., a first verify voltage applied during the first verify operation in the first verify phase), while the high verify level VH may be a fine verify voltage (e.g., a second verify voltage applied during the second verify operation in the second verify phase).”; that programming often uses multiple rates of programming with large jumps (coarse) and smaller voltage jumps (fine programming)).
In view of the teachings of Zhao it would have been obvious for a person of ordinary skill in the art to apply the teachings of Zhao to Lee before the effective filing date of the claimed invention in order to teach programming memory cells. The teachings of Zhao, in the same or in a similar field of endeavor with Lee, can combine Zhao’s explicit voltages used in ISPP and Lee’s less explicit programming operations. The two programming operations using slightly differing voltages for wordlines and bitlines perform the same functions as they perform separately and being no more “the combining of prior art elements according to known methods to yield predictable results” (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)).
Regarding claim 18, Lee teaches the method according to claim 10.
Lee does not explicitly teach wherein verifying that the selected memory cells have been programmed successfully comprises setting a predefined bias voltage to bit lines to which the selected memory cells are coupled, so that the bias voltage depends on the verification voltage..
Zhao teaches wherein verifying that the selected memory cells have been programmed successfully comprises setting a predefined bias voltage to bit lines to which the selected memory cells are coupled, so that the bias voltage depends on the verification voltage. (Zhao, fig 8A, “[0108] In some implementations, the low verify level VL may be a coarse verify voltage (e.g., a first verify voltage applied during the first verify operation in the first verify phase), while the high verify level VH may be a fine verify voltage (e.g., a second verify voltage applied during the second verify operation in the second verify phase). [0110] The method applies incremental-step-pulse programming (ISPP) with multiple bit line bias voltages (e.g., 3 bit line (3BL), 4 bit line (4BL), or more bit line bias voltages)… Step 804: Compare the threshold voltage Vt of the memory cell with the high verify level VH and/or the low verify level VL; if the threshold voltage Vt of the memory cell is higher than the high verify level VH, proceed to Step 806; if the threshold voltage Vt of the memory cell is higher than the low verify level VL but lower than the high verify level VH, proceed to Step 808; if the threshold voltage Vt of the memory cell is lower than the low verify level VL, proceed to Step 810: Step 806:”; that the VL (coarse programming) and VH (fine programming) can be coordinated with a bias voltage applied to the bit line to adjust the programming speed for a memory cell).
In view of the teachings of Zhao it would have been obvious for a person of ordinary skill in the art to apply the teachings of Zhao to Lee before the effective filing date of the claimed invention in order to teach programming memory cells. The teachings of Zhao, in the same or in a similar field of endeavor with Lee, can combine Zhao’s explicit voltages used in ISPP and Lee’s less explicit programming operations. The two programming operations using slightly differing voltages for wordlines and bitlines perform the same functions as they perform separately and being no more “the combining of prior art elements according to known methods to yield predictable results” (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)).
Conclusion
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/Donald HB Braswell/ Primary Examiner, Art Unit 2825