DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-21 are pending in this application.
Response to Arguments
Applicant's arguments filed 05/26/2026 have been fully considered but they are not persuasive. Applicant amended claim 1 to include “second supply voltage terminal”. In view of applicant’s amendment, first and second voltage terminals have been mapped to terminal connected to line 19 and terminal connected to resistor 31 of fig.1 in prior art Bangs (US 20010004219 A1). Please see rejection below for further details.
The newly added claim 21 is also taught by prior art Bangs as discussed below.
Response to Amendment
The amendment to the claims filed on 05/26/2026 does not comply with the requirements of 37 CFR 1.121(c) because “Amendments to a claim must be made by rewriting the entire claim with all changes (e.g., additions and deletions)”. Amendments to the claims filed on or after July 30, 2003 must comply with 37 CFR 1.121(c) which states:
(c) Claims. Amendments to a claim must be made by rewriting the entire claim with all changes (e.g., additions and deletions) as indicated in this subsection, except when the claim is being canceled. Each amendment document that includes a change to an existing claim, cancellation of an existing claim or addition of a new claim, must include a complete listing of all claims ever presented, including the text of all pending and withdrawn claims, in the application. The claim listing, including the text of the claims, in the amendment document will serve to replace all prior versions of the claims, in the application. In the claim listing, the status of every claim must be indicated after its claim number by using one of the following identifiers in a parenthetical expression: (Original), (Currently amended), (Canceled), (Withdrawn), (Previously presented), (New), and (Not entered).
(1) Claim listing. All of the claims presented in a claim listing shall be presented in ascending numerical order. Consecutive claims having the same status of “canceled” or “not entered” may be aggregated into one statement (e.g., Claims 1–5 (canceled)). The claim listing shall commence on a separate sheet of the amendment document and the sheet(s) that contain the text of any part of the claims shall not contain any other part of the amendment.
(2) When claim text with markings is required. All claims being currently amended in an amendment paper shall be presented in the claim listing, indicate a status of “currently amended,” and be submitted with markings to indicate the changes that have been made relative to the immediate prior version of the claims. The text of any added subject matter must be shown by underlining the added text. The text of any deleted matter must be shown by strike-through except that double brackets placed before and after the deleted characters may be used to show deletion of five or fewer consecutive characters. The text of any deleted subject matter must be shown by being placed within double brackets if strike-through cannot be easily perceived. Only claims having the status of “currently amended,” or “withdrawn” if also being amended, shall include markings. If a withdrawn claim is currently amended, its status in the claim listing may be identified as “withdrawn—currently amended.”
(3) When claim text in clean version is required. The text of all pending claims not being currently amended shall be presented in the claim listing in clean version, i.e., without any markings in the presentation of text. The presentation of a clean version of any claim having the status of “original,” “withdrawn” or “previously presented” will constitute an assertion that it has not been changed relative to the immediate prior version, except to omit markings that may have been present in the immediate prior version of the claims of the status of “withdrawn” or “previously presented.” Any claim added by amendment must be indicated with the status of “new” and presented in clean version, i.e., without any underlining.
(4) When claim text shall not be presented; canceling a claim.
(i) No claim text shall be presented for any claim in the claim listing with the status of “canceled” or “not entered.”
(ii) Cancellation of a claim shall be effected by an instruction to cancel a particular claim number. Identifying the status of a claim in the claim listing as “canceled” will constitute an instruction to cancel the claim.
(5) Reinstatement of previously canceled claim. A claim which was previously canceled may be reinstated only by adding the claim as a “new” claim with a new claim number.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 7 and 21 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Bangs (US 20010004219 A1).
Regarding claim 1, Bangs teaches an apparatus (i.e. LVDS receiver, fig.1), comprising:
a first comparator (i.e. second amplifier 5, fig.1) having first and second inputs (i.e. + and – inputs of 5, fig.1), a first control input (e.g. input connected to line 23, fig.1), an output (e.g. output of 5 connected to resistor 29 or 31, fig.1), and first and second supply voltage terminals (e.g. terminal connected to line 19 and terminal connected to resistor 31, fig.1);
a second comparator (i.e. first amplifier 3, fig.1) having first and second inputs (i.e. + and – inputs of 3, fig.1), a second control input (e.g. input connected to line 21, fig.1), and an output (e.g. output of 3 connected to resistor 29 or 31, fig.1), the first input of the second comparator coupled to the first input of the first comparator (e.g. + of both 3 and 5 are coupled, fig.1), the second input of the second comparator coupled to the second input of the first comparator (e.g. - of both 3 and 5 are coupled, fig.1); and
a logic circuit (e.g. circuit comprising third and fourth amplifier 15 and 17, fig.1) having an input (e.g. input connected to 11, fig.1), a first output (e.g. output connected to line 19, fig.1), a second output (e.g. output connected to line 23, fig.1), and a third output (e.g. output connected to line 21, fig.1), the input of the logic circuit coupled to the first supply voltage terminal (e.g. 11 is connected to supply voltage of 5 (connected to 31), via 15 and 5, fig.1) and to the first inputs of the first and second comparators (e.g. 11 is connected to + of 3 and 5 via resistor R, fig.1), the first output coupled to the second supply voltage terminal of the first comparator (e.g. 19 couples 15 and 5, fig.1), the second output coupled to the first control input (e.g. 23 couples 17 and 5, fig.1), and the third output coupled to second control input (e.g. 21 couples 17 and 3, fig.1).
Regarding claim 7, Bangs teaches the apparatus of claim 1, wherein the logic circuit is configured to:
enable the output of the first comparator when a voltage at the first input is more than a threshold level above a voltage at the first output ([0028], common mode voltages in the range from 0 v to approximately 1.2V); and
enable the output of the second comparator when a voltage at the first input is less than the threshold level above the voltage at the first output ([0027], common mode voltages in the range from approximately 1.2V to 2.4V);
wherein the threshold level is within a range for which both the first and second comparators are configured to be operational (e.g. range of 0V to 2.4V, [0027]-[0028]).
Regarding claim 21, Bangs teaches an apparatus (i.e. LVDS receiver, fig.1), comprising:
a first comparator (i.e. second amplifier 5, fig.1) having first and second inputs (i.e. + and – inputs of 5, fig.1), a control input (e.g. input connected to line 23, fig.1), and a supply voltage terminal (e.g. terminal connected to line 19, fig.1);
a second comparator (i.e. first amplifier 3, fig.1) having first and second inputs (i.e. + and – inputs of 3, fig.1), a control input (e.g. input connected to line 21, fig.1), the first input of the second comparator coupled to the first input of the first comparator (e.g. + of both 3 and 5 are coupled, fig.1), the second input of the second comparator coupled to the second input of the first comparator (e.g. - of both 3 and 5 are coupled, fig.1); and
a logic circuit (e.g. circuit comprising third and fourth amplifier 15 and 17, fig.1) having an input (e.g. input connected to 11, fig.1) coupled to the first inputs of the first and second comparators (e.g. 11 is connected to + of 3 and 5 via resistor R, fig.1), a first output (e.g. output connected to line 19, fig.1) coupled to the supply voltage terminal of the first comparator (e.g. 19 couples 15 and 5, fig.1), and a second outputs (e.g. output connected to line 23 and line 21, fig.1) coupled to respective control inputs of the first and second comparators (e.g. 23 couples 17 and 5, 21 couples 17 and 3, fig.1), the logic circuit configurable to:
enable the first comparator and disable the second comparator ([0036], the first amplifier 3 will be fully turned OFF, whereas the second amplifier 5 will be fully turned ON) responsive to a voltage difference between the input of the logic circuit and the first output being above a threshold ([0028], common mode voltages in the range from 0 v to approximately 1.2V); and
enable the second comparator and disable the first comparator ([0034], the first amplifier 3 will be fully turned ON, while the second amplifier 5 will be fully turned OFF) responsive to the voltage difference being below the threshold ([0027], common mode voltages in the range from approximately 1.2V to 2.4V).
Allowable Subject Matter
Claims 10-20 are allowed.
Claims 2-6 and 8-9 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 2, Bangs (US 20010004219 A1) teaches the apparatus of claim 1.
Bangs does not teach, wherein the logic circuit includes: a voltage regulator having an input coupled to the first input of the logic circuit and having an output coupled to the first output of the logic circuit; and a power-on reset (POR) circuit having a first terminal coupled to the first input of the logic circuit, a second terminal coupled to the output of the voltage regulator, and an output coupled to the second output of the logic circuit.
Prior art Hulfachor (US 8593119 B2), Chou (US 20230127395 A1), Telefus (US 20200366079 A1) and Ehrenreich (US 20080048729 A1) have been found to be the closest prior art.
However, none of the prior art, taken singly or in combination, teach “wherein the logic circuit includes: a voltage regulator having an input coupled to the first input of the logic circuit and having an output coupled to the first output of the logic circuit; and a power-on reset (POR) circuit having a first terminal coupled to the first input of the logic circuit, a second terminal coupled to the output of the voltage regulator, and an output coupled to the second output of the logic circuit.”
Claim 3 is indicated as allowable, as it depends on allowable claim 2.
Regarding claim 4, Bangs (US 20010004219 A1) teaches the apparatus of claim 1.
Bangs does not teach, wherein the second comparator includes:
a first current source circuit;
a first current mirror having a first mirror input and a first mirror output;
a first switch coupled between the first current source circuit and the first mirror input, the first switch having a first switch control input;
an input stage circuit having a first input coupled to the first input of the second comparator, a second input coupled to the second input of the second comparator, and a first output coupled to the first switch control input;
a second current mirror having a second mirror input and a second mirror output, the second mirror input coupled to the first mirror output; and
a second current source circuit coupled to the second mirror output.
Chou (US 20230127395 A1) teaches in a similar field of endeavor of overcurrent protection circuit, a second comparator includes:
a first current source circuit (e.g. circuit comprising load switch 11, fig.1);
a first current mirror (i.e. first mirror circuit 12, fig.2) having a first mirror input (e.g. VDD to SW1 and R1, fig.2) and a first mirror output (e.g. output at detection point 201, fig.2);
a second current mirror (i.e. mirror circuit 13, fig.2) having a second mirror input (e.g. VDD to R2, fig.2) and a second mirror output (e.g. output at point 202, fig.2), the second mirror input coupled to the first mirror output (e.g. coupled at Vctrl and 14, fig.2);
Bangs does not teach, a first switch coupled between the first current source circuit and the first mirror input, the first switch having a first switch control input;
an input stage circuit having a first input coupled to the first input of the second comparator, a second input coupled to the second input of the second comparator, and a first output coupled to the first switch control input; and
a second current source circuit coupled to the second mirror output.
Prior art Sievers (US 20220224323 A1), Errico (US 20220190585 A1), Telefus (US 20200366079 A1) and Ehrenreich (US 20080048729 A1) have been found to be the closest prior art.
However, none of the prior art, taken singly or in combination, teach “a first switch coupled between the first current source circuit and the first mirror input, the first switch having a first switch control input;
an input stage circuit having a first input coupled to the first input of the second comparator, a second input coupled to the second input of the second comparator, and a first output coupled to the first switch control input; and
a second current source circuit coupled to the second mirror output.”
Claims 5-6 are indicated as allowable, as they depend on allowable claim 4.
Regarding claim 8, Bangs (US 20010004219 A1) teaches the apparatus of claim 1.
Bangs does not teach, further comprising:
a driver having an input and an output;
a logic gate having first and second inputs and an output, the output of the logic gate coupled to the input of the driver, the first input of the logic gate coupled to the output of the first comparator, and the second input of the logic gate coupled to the output of the second comparator;
a transistor having first and second terminals and a control input, the control input coupled to the output of the driver; and
a resistor having first and second resistor terminals, the first resistor terminal coupled to the second terminal of the transistor and to the second inputs of the first and second comparators, and the second resistor terminal coupled to the first inputs of the first and second comparators.
Prior art Hulfachor (US 8593119 B2), Chou (US 20230127395 A1), Telefus (US 20200366079 A1), Sievers (US 20220224323 A1), Errico (US 20220190585 A1) and Ehrenreich (US 20080048729 A1) have been found to be the closest prior art.
However, none of the prior art, taken singly or in combination, teach “a driver having an input and an output;
a logic gate having first and second inputs and an output, the output of the logic gate coupled to the input of the driver, the first input of the logic gate coupled to the output of the first comparator, and the second input of the logic gate coupled to the output of the second comparator;
a transistor having first and second terminals and a control input, the control input coupled to the output of the driver; and
a resistor having first and second resistor terminals, the first resistor terminal coupled to the second terminal of the transistor and to the second inputs of the first and second comparators, and the second resistor terminal coupled to the first inputs of the first and second comparators.”
Claim 9 is indicated as allowable, as it depends on allowable claim 8.
Regarding claim 10, it is allowed for the same reasons as stated above for claim 4.
Claims 11-16 are allowed, as they depend on claim 10.
Regarding claim 17, it is allowed for the same reasons as stated above for claim 4.
Claims 18-20 are allowed, as they depend on claim 17.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SREEYA SREEVATSA whose telephone number is (571)272-8304. The examiner can normally be reached M-F 8am-5pm ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Thienvu V Tran can be reached at (571) 270-1276. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SREEYA SREEVATSA/Primary Examiner, Art Unit 2838 06/30/2026
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