DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are pending in this application.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) were submitted on 07/17/2024 and 02/28/2025. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1 and 7 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Bangs (US 20010004219 A1).
Regarding claim 1, Bangs teaches an apparatus (i.e. LVDS receiver, fig.1), comprising:
a first comparator (i.e. second amplifier 5, fig.1) having first and second inputs (i.e. + and – inputs of 5, fig.1), a first control input (e.g. input connected to line 23, fig.1), an output (e.g. output of 5 connected to resistor 29 or 31, fig.1), and a supply voltage terminal (e.g. terminal connected to line 19, fig.1);
a second comparator (i.e. first amplifier 3, fig.1) having first and second inputs (i.e. + and – inputs of 3, fig.1), a second control input (e.g. input connected to line 21, fig.1), and an output (e.g. output of 3 connected to resistor 29 or 31, fig.1), the first input of the second comparator coupled to the first input of the first comparator (e.g. + of both 3 and 5 are coupled, fig.1), the second input of the second comparator coupled to the second input of the first comparator (e.g. - of both 3 and 5 are coupled, fig.1); and
a switchover logic circuit (e.g. circuit comprising third and fourth amplifier 15 and 17, fig.1) having an input (e.g. input connected to 11, fig.1), a first output (e.g. output connected to line 19, fig.1), a second output (e.g. output connected to line 23, fig.1), and a third output (e.g. output connected to line 21, fig.1), the input of the switchover logic circuit coupled to the first inputs of the first and second comparators (e.g. 11 is connected to + of 3 and 5 via resistor R, fig.1), the first output coupled to the supply voltage terminal of the first comparator (e.g. 19 couples 15 and 5, fig.1), the second output coupled to the first control input (e.g. 23 couples 17 and 5, fig.1), and the third output coupled to second control input (e.g. 21 couples 17 and 3, fig.1).
Regarding claim 7, Bangs teaches the apparatus of claim 1, wherein the switchover logic circuit is configured to:
enable the output of the first comparator when a voltage at the first input is more than a threshold level above a voltage at the first output ([0028], common mode voltages in the range from 0 v to approximately 1.2V); and
enable the output of the second comparator when a voltage at the first input is less than the threshold level above the voltage at the first output ([0027], common mode voltages in the range from approximately 1.2V to 2.4V);
wherein the threshold level is within a range for which both the first and second comparators are configured to be operational (e.g. range of 0V to 2.4V, [0027]-[0028]).
Allowable Subject Matter
Claims 10-20 are allowed.
Claims 2-6 and 8-9 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 2, Bangs (US 20010004219 A1) teaches the apparatus of claim 1.
Bangs does not teach, wherein the switchover logic circuit includes: a voltage regulator having an input coupled to the first input of the switchover logic circuit and having an output coupled to the first output of the switchover logic circuit; and a power-on reset (POR) circuit having a first terminal coupled to the first input of the switchover logic circuit, a second terminal coupled to the output of the voltage regulator, and an output coupled to the second output of the switchover logic circuit.
Prior art Hulfachor (US 8593119 B2), Chou (US 20230127395 A1), Telefus (US 20200366079 A1) and Ehrenreich (US 20080048729 A1) have been found to be the closest prior art.
However, none of the prior art, taken singly or in combination, teach “wherein the switchover logic circuit includes: a voltage regulator having an input coupled to the first input of the switchover logic circuit and having an output coupled to the first output of the switchover logic circuit; and a power-on reset (POR) circuit having a first terminal coupled to the first input of the switchover logic circuit, a second terminal coupled to the output of the voltage regulator, and an output coupled to the second output of the switchover logic circuit.”
Claim 3 is indicated as allowable, as it depends on allowable claim 2.
Regarding claim 4, Bangs (US 20010004219 A1) teaches the apparatus of claim 1.
Bangs does not teach, wherein the second comparator includes:
a first current source circuit;
a first current mirror having a first mirror input and a first mirror output;
a first switch coupled between the first current source circuit and the first mirror input, the first switch having a first switch control input;
an input stage circuit having a first input coupled to the first input of the second comparator, a second input coupled to the second input of the second comparator, and a first output coupled to the first switch control input;
a second current mirror having a second mirror input and a second mirror output, the second mirror input coupled to the first mirror output; and
a second current source circuit coupled to the second mirror output.
Chou (US 20230127395 A1) teaches in a similar field of endeavor of overcurrent protection circuit, a second comparator includes:
a first current source circuit (e.g. circuit comprising load switch 11, fig.1);
a first current mirror (i.e. first mirror circuit 12, fig.2) having a first mirror input (e.g. VDD to SW1 and R1, fig.2) and a first mirror output (e.g. output at detection point 201, fig.2);
a second current mirror (i.e. mirror circuit 13, fig.2) having a second mirror input (e.g. VDD to R2, fig.2) and a second mirror output (e.g. output at point 202, fig.2), the second mirror input coupled to the first mirror output (e.g. coupled at Vctrl and 14, fig.2);
Bangs does not teach, a first switch coupled between the first current source circuit and the first mirror input, the first switch having a first switch control input;
an input stage circuit having a first input coupled to the first input of the second comparator, a second input coupled to the second input of the second comparator, and a first output coupled to the first switch control input; and
a second current source circuit coupled to the second mirror output.
Prior art Sievers (US 20220224323 A1), Errico (US 20220190585 A1), Telefus (US 20200366079 A1) and Ehrenreich (US 20080048729 A1) have been found to be the closest prior art.
However, none of the prior art, taken singly or in combination, teach “a first switch coupled between the first current source circuit and the first mirror input, the first switch having a first switch control input;
an input stage circuit having a first input coupled to the first input of the second comparator, a second input coupled to the second input of the second comparator, and a first output coupled to the first switch control input; and
a second current source circuit coupled to the second mirror output.”
Claims 5-6 are indicated as allowable, as they depend on allowable claim 4.
Regarding claim 8, Bangs (US 20010004219 A1) teaches the apparatus of claim 1.
Bangs does not teach, further comprising:
a driver having an input and an output;
a logic gate having first and second inputs and an output, the output of the logic gate coupled to the input of the driver, the first input of the logic gate coupled to the output of the first comparator, and the second input of the logic gate coupled to the output of the second comparator;
a transistor having first and second terminals and a control input, the control input coupled to the output of the driver; and
a resistor having first and second resistor terminals, the first resistor terminal coupled to the second terminal of the transistor and to the second inputs of the first and second comparators, and the second resistor terminal coupled to the first inputs of the first and second comparators.
Prior art Hulfachor (US 8593119 B2), Chou (US 20230127395 A1), Telefus (US 20200366079 A1), Sievers (US 20220224323 A1), Errico (US 20220190585 A1) and Ehrenreich (US 20080048729 A1) have been found to be the closest prior art.
However, none of the prior art, taken singly or in combination, teach “a driver having an input and an output;
a logic gate having first and second inputs and an output, the output of the logic gate coupled to the input of the driver, the first input of the logic gate coupled to the output of the first comparator, and the second input of the logic gate coupled to the output of the second comparator;
a transistor having first and second terminals and a control input, the control input coupled to the output of the driver; and
a resistor having first and second resistor terminals, the first resistor terminal coupled to the second terminal of the transistor and to the second inputs of the first and second comparators, and the second resistor terminal coupled to the first inputs of the first and second comparators.”
Claim 9 is indicated as allowable, as it depends on allowable claim 8.
Regarding claim 10, it is allowed for the same reasons as stated above for claim 4.
Claims 11-16 are allowed, as they depend on claim 10.
Regarding claim 17, it is allowed for the same reasons as stated above for claim 4.
Claims 18-20 are allowed, as they depend on claim 17.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SREEYA SREEVATSA whose telephone number is (571)272-8304. The examiner can normally be reached M-F 8am-5pm ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Thienvu V Tran can be reached at (571) 270-1276. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/SREEYA SREEVATSA/ Primary Examiner, Art Unit 2838 03/03/2026