DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Park et al. (hereinafter “Park” US 2017 / 0127512).
As pertaining to Claim 1, Park discloses (see Fig. 1 and Fig. 3) a display device (100; see Page 3, Para. [0055] and Page 4, Para. [0064]-[0067]) comprising:
a display panel (110);
a printed circuit board (130); and
a circuit film (120) disposed between and connected to the display panel (110) and the printed circuit board (130), wherein the circuit film (120) includes an input side bonding area (IPA) connected to the printed circuit board (130) and an output side bonding area (OPA) connected to the display panel (110),
wherein the input side bonding area (IPA) includes a plurality of input pads (IPD) connected (i.e., via (125)) to the output side bonding area (OPA),
wherein the plurality of input pads (IPD) are arranged in two rows (see (IR1, IR2); and see Page 4, Para. [0069]-[0074]).
As pertaining to Claim 2, Park discloses (see Fig. 1 and Fig. 3) that the output side bonding area (OPA) includes a plurality of output pads (OPD), wherein the plurality of output pads (OPD) are arranged in two rows (see (OR1, OR2); and see Page 4, Para. [0069]-[0074]).
As pertaining to Claim 3, Park discloses (see Fig. 1 and Fig. 3) that the plurality of input pads (IPD) of the input side bonding area (IPA) of the circuit film (120) includes:
first input pads (IPD) respectively disposed in both opposing sides (i.e., left and right sides) of the input side bonding area (IPA) and arranged in a first row (IR1);
second input pads (IPD) respectively disposed in both opposing sides (i.e., left and right sides) of the input side bonding area (IPA) and arranged in a second row (IR2); and
third input pads (IPD) disposed in a center of the input side bonding area (IPA), and arranged in the first row (IR1), the second row (IR2) or a single row as a combination of the first and second rows (see (IR1, IR2); and see Page 4, Para. [0069]-[0074]).
As pertaining to Claim 4, Park discloses (see Fig. 1 and Fig. 3) that each of the first input pad (see (IPD) at left and right sides of (IPA)) and the second input pad (see (IPD) at left and right sides of (IPA)) is bonded to a pad (i.e., a pad part) of the printed circuit board (130) and is directly connected (i.e., via (125)) to the output side bonding area (OPA; see Page 4, Para. [0069]-[0074]).
As pertaining to Claim 5, Park discloses (see Fig. 1 and Fig. 3) that the first input pad (see (IPD) at left and right sides of (IPA)) and the second input pad (see (IPD) at left and right sides of (IPA)) are configured to receive a plurality of voltages and a plurality of control signals from the printed circuit board (130; see Page 4, Para. [0066]-[0074]).
As pertaining to Claim 6, Park discloses (see Fig. 1 and Fig. 3) that the third input pad (see (IPD) at the center of (IPA)) is bonded to a pad of the printed circuit board (130) and is connected to the output side bonding area (OPA) through a source driver (see (125)) mounted on a center of the circuit film (120; see Page 4, Para. [0069]-[0074]).
As pertaining to Claim 7, Park discloses (see Fig. 1 and Fig. 3) that the third input pad (see (IPD) at the center of (IPA)) is configured to receive a digital signal from the printed circuit board (130; see Page 4, Para. [0066]-[0074]).
As pertaining to Claim 8, Park discloses (see Fig. 1 and Fig. 3) that the output side bonding area (OPA) of the circuit film (120) includes:
first output pads (OPD) respectively disposed in two opposing sides (i.e., left and right sides) of the output side bonding area (OPA) and arranged in a first row (OR2);
second output pads (OPD) respectively disposed in two opposing sides (i.e., left and right sides) of the output side bonding area (OPA) and arranged in a second row (OR1);
third output pads (OPD) arranged in the first row (OR2) and disposed in a center of the output side bonding area (OPA); and
fourth output pads (OPD) arranged in the second row (OR1) and disposed in the center of the output side bonding area (OPA; see Page 4, Para. [0069]-[0074]).
As pertaining to Claim 9, Park discloses (see Fig. 1 and Fig. 3) that each of the first output pad (see (OPD) at left and right sides of (OPA)) and the second output pad (see (OPD) at left and right sides of (OPA)) is bonded to the pad of the display panel (110) and is directly connected to the input side bonding area (IPA; see Page 4, Para. [0069]-[0074]).
As pertaining to Claim 10, Park discloses (see Fig. 1 and Fig. 3) that the third output pad (see (OPD) at a center of (OPA) in row (OR2)) and the fourth output pad (see (OPD) at a center of (OPA) in row (OR1)) are bonded to a pad of the display panel (110) and are connected to the input side bonding area (IPA) through a source driver (125) mounted on a center of the circuit film (120; see Page 4, Para. [0069]-[0074]).
As pertaining to Claim 11, Park discloses (see Fig. 1 and Fig. 3) that the first input pad (see (IPD) at left and right sides of (IPA)) and the second input pad (see (OPD) at left and right sides of (OPA)) are arranged in a staggered manner based on a reference line (i.e., a vertical line), the first output pad (see (OPD) at left and right sides of (OPA)) and the second output pad (see (OPD) at left and right sides of (OPA)) are arranged in a staggered manner based on the reference line (i.e., the vertical line), and the third input pad (see (IPD) at the center of (IPA)), the third output pad (see (OPD) at a center of (OPA) in row (OR2)) and the fourth output pad (see (OPD) at a center of (OPA) in row (OR1)) are arranged in a same column (see Fig. 3; and see Page 4, Para. [0069]-[0074]).
As pertaining to Claim 12, Park discloses (see Fig. 1 and Fig. 3) that the first input pad (see (IPD) at left and right sides of (IPA)) and the second input pad (see (OPD) at left and right sides of (OPA)) are located in different layers (i.e., rows) and in a same column, and the first output pad (see (OPD) at left and right sides of (OPA)) and the second output pad (see (OPD) at left and right sides of (OPA)) are located in different layers (i.e., rows) and in a same column (see Page 4, Para. [0069]-[0074]).
As pertaining to Claim 13, Park discloses (see Fig. 1 and Fig. 3) a display device (100; see Page 3, Para. [0055] and Page 4, Para. [0064]-[0067]) comprising:
a printed circuit board (130) including a pad (i.e., a pad part) for outputting a plurality of voltages and a plurality of control signals;
a display panel (110) including a display area (DA) and a non-display area (BA, MA) around the display area (DA), wherein a plurality of sub-pixels (PX) are disposed in the display area (DA), and a pad (i.e., a pad part) is disposed in the non-display area (BA, MA);
a circuit film (120) including an input side bonding area (IPA) bonded to the pad (i.e., the pad part) of the printed circuit board (130) and an output side bonding area (OPA) bonded to the pad (i.e., the pad part) of the display panel (110), wherein the input side bonding area (IPA) includes a plurality of input pads (IPD), wherein at least two of the plurality of input pads (IPD) are respectively disposed in at least two rows (IR1, IR2); and
a source driver (125) mounted on the circuit film (120), wherein the source driver (125) is electrically connected to the printed circuit board (130) via the input side bonding area (IPA), and is electrically connected to the display panel (110) via the output side bonding area (OPA; see Page 4, Para. [0069]-[0074]).
As pertaining to Claim 14, Park discloses (see Fig. 1 and Fig. 3) that the output side bonding area (OPA) of the circuit film (120) includes a plurality of output pads (OPD) arranged in two rows (see (OR1, OR2); and see Page 4, Para. [0069]-[0074]).
As pertaining to Claim 15, Park discloses (see Fig. 1 and Fig. 3) that the input side bonding area (IPA) includes:
first input pads (IPD) arranged in a first row (IR1);
second input pads (IPD) arranged in a second row (IR2); and
third input pads (IPD) arranged in the first row (IR1), the second row (IR2) or a single row as a combination of the first and second rows (see (IR1, IR2); and see Page 4, Para. [0069]-[0074]).
As pertaining to Claim 16, Park discloses (see Fig. 1 and Fig. 3) that the first input pads (IPD) are respectively disposed in two opposing sides (i.e., left and right sides) of the input side bonding area (IPA),
wherein the second input pads (IPD) are respectively disposed in two opposing sides (i.e., left and right sides) of the input side bonding area (IPA),
wherein the third input pads (IPD) are disposed in a center of the input side bonding area (IPA; see Page 4, Para. [0069]-[0074]).
As pertaining to Claim 17, Park discloses (see Fig. 1 and Fig. 3) that each of the first input pad (see (IPD) at left and right sides of (IPA)) and the second input pad (see (IPD) at left and right sides of (IPA)) is directly connected (i.e., via (125)) to the output side bonding area (OPA) of the circuit film (120) via each connection wiring (see (ISL, OSL)), and the third input pad (see (IPD) at a center of (IPA)) is connected to the output side bonding area (OPA) of the circuit film (120) via the source driver (125; again, see Page 4, Para. [0069]-[0074]).
As pertaining to Claim 18, Park discloses (see Fig. 1 and Fig. 3) that the output side bonding area (OPA) includes:
first output pads (OPD) arranged in a first row (OR2);
second output pads (OPD) arranged in a second row (OR1);
third output pads (OPD) arranged in the first row (OR2); and
fourth output pads (OPD) arranged in the second row (OR1; see Page 4, Para. [0069]-[0074]).
As pertaining to Claim 19, Park discloses (see Fig. 1 and Fig. 3) that the first output pads (OPD) are respectively disposed in two opposing sides (i.e., left and right sides) of the output side bonding area (OPA),
wherein the second output pads (OPD) are respectively disposed in two opposing sides (i.e., left and right sides) of the output side bonding area (OPA),
wherein the third output pads (OPD) are disposed in a center of the output side bonding area (OPA); and
wherein the fourth output pads (OPD) and disposed in the center of the output side bonding area (OPA; see Page 4, Para. [0069]-[0074]).
As pertaining to Claim 20, Park discloses (see Fig. 1 and Fig. 3) that the first input pad (see (IPD) at left and right sides of (IPA)) and the second input pad (see (OPD) at left and right sides of (OPA)) are arranged in a staggered manner based on a reference line (i.e., a vertical line), the first output pad (see (OPD) at left and right sides of (OPA)) and the second output pad (see (OPD) at left and right sides of (OPA)) are arranged in a staggered manner based on the reference line (i.e., the vertical line), and the third input pad (see (IPD) at the center of (IPA)), the third output pad (see (OPD) at a center of (OPA) in row (OR2)) and the fourth output pad (see (OPD) at a center of (OPA) in row (OR1)) are arranged in a same column (see Fig. 3; and see Page 4, Para. [0069]-[0074]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Hong et al. (US 2023 / 0213974), submitted by the applicant via Information Disclosure Statement (IDS) on 17 July 2024, discloses (see Fig. 5) a circuit film having an input side bonding area and an output side bonding area.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JASON M MANDEVILLE whose telephone number is (571)270-3136. The examiner can normally be reached Mon - Fri 7:30AM-4:00PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chanh Nguyen can be reached at 571-272-7772. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JASON M MANDEVILLE/Primary Examiner, Art Unit 2623
