Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
2. Claims 13-15 withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention II, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 7/14/2025.
3. Claims 1-15 are pending with claims 13-15 withdrawn. Bolded claim language below regards newly amended subject matter with a corresponding new rejection citation. Newly amended subject matter that is not bolded does not comprise a new rejection citation (utilizes previous interpretation that is unchanged in view of the new language) or is a newly added claim.
Claim Rejections - 35 USC § 103
4. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kang et al. (US Patent Application Publication 2021/0287579), herein after referred to as Kang, in view of Leshniak (US Patent Application Publication 2013/0207548), and in further view of Liao et al. (US patent Application Publication 2022/0415247), herein after referred to as Liao.
Regarding independent claim 1, Kang discloses a display device (Figure 1 reference display 1000.), comprising:
a display panel (100) including a plurality of sub pixels (PX);
a first light emitting diode in each of the plurality of sub pixels (Figure 3 reference pixel PX 10 depicting a single instance of the plurality of sub pixels. Figure 3 depicts a first light emitting diode LD1.);
a second light emitting diode (LD2) that is connected to the first light emitting diode (LD1) in series (Figure 3 reference cathode of LD1 directly connected to anode of LD2 via node N3 to form a series connection as described in paragraphs [0076] and [0078].);
a first control transistor that is connected to the first light emitting diode in parallel, the first control transistor turned on by a first control signal; and
a second control transistor (T2) that is connected to the second light emitting diode (LD2) in parallel (Figure 3 depicts T2 and LD2 with respective first electrode and anode directly and commonly connected to node N3 and respective second electrode and cathode directly and commonly connected to VSS together T2 and LD2, as described in paragraphs [0078] and [0085]-[0086] forming a parallel connection.), the second control transistor (T2) turned on by a second control signal (CCLi) (Figure 3 decpits T2 with gate electrode directly connected to CCLi described in paragraph [0086] to turn on T2.),
[ ].
Kang discloses T2 forms a bypass between LD1 and VSS bypassing LD2 as described in paragraph [0086]. Paragraph [0163] describes that the pixel 12 may include at least one transistor corresponding thereto to form a bypass, implying more than one transistor and bypass may be formed. However, while Kang implies an additional control transistor to form a bypass it is not explicitly stated. Therefore, Kang does not specifically disclose a first control transistor that is connected to the first light emitting diode in parallel, the first control transistor turned on by a first control signal.
Leshniak disclosed an improved LED (Figure 3C, abstract, and paragraphs [0030] and [0081].), comprising:
a first light emitting diode (North most LED die 104, as oriented in figure 3C, herein after referred to as 104a with additional components following suit (label of a being the northern most component as oriented in the figure).) in each of the plurality of sub pixels (Figure 3 reference pixel PX 10 depicting a single instance of the plurality of sub pixels. Figure 3 depicts a first light emitting diode LD1.);
a second light emitting diode (104b) that is connected to the first light emitting diode (104a) in series (paragraph [0071]);
a first control transistor (324a) that is connected to the first light emitting diode (104a) in parallel (Figure 3C depicts a parallel connection between 103 and respective 324 forming a bypass as described in paragraph [0082].), the first control transistor (104a) turned on by a first control signal (Microcontroller 320 described in paragraph [0082] to send signals to open/close switches 324.); and
a second control transistor (324b) that is connected to the second light emitting diode (104b) in parallel (Figure 3C depicts a parallel connection between 103 and respective 324 forming a bypass as described in paragraph [0082].).
It would have been obvious to one skilled in the art before the effective filing date of the current application to enable Kang’s first LED LD1 with the known technique of a first control transistor that is connected to the first light emitting diode in parallel, the first control transistor turned on by a first control signal yielding the predictable results of forming a bypass as disclosed by Leshniak (paragraph [0082]) allowing inspection of the second LD2 of Kang (paragraph [0086]).
Kang does not specifically disclose wherein the first light emitting diode and the second light emitting diode emit light of a same color.
Liao discloses wherein the first light emitting diode and the second light emitting diode emit light of a same color (Figure 2A reference series connected LEDs L1 and L2 described in paragraph [0044] to emit the same color.).
It would have been obvious to one skilled in the art before the effective filing date of the current application to enable Kang’s first LED LD1 and second LED LD2 with the known technique of emit light of a same color yielding the predictable results of enabling varying brightness of the same color as disclosed by Liao (paragraph [0047]).
Regarding claim 2, Kang discloses the display device according to claim 1, wherein the first light emitting diode (LD1) and the second light emitting diode (LD2) emit light by turns (Paragraph [0086] describes to bypass LD2 when LD1 is inspected. Paragraph [0113] describes inspection to include emitting light. Since LD2 is bypassed in this inspection step this described emitting light in turns.).
Regarding claim 3, Kang and Leshniak discloses the display device according to claim 2, wherein the first control transistor (Leshniak 104a disposed in a parallel connection position with LD1 of Kang) is turned off and the second control transistor (T2) is turned on while the first light emitting diode (LD1) emits light (Paragraph [0086] describes T2 to be on to form a bypass when LD1 is inspected/turned on emitting light (paragraph [0113]). This inherently describes the first control transistor 104a to be turn off so as to not bypass LD1.).
Regarding claim 4, Kang discloses the display device according to claim 3, wherein a driving current flows from the first light emitting diode (LD1) to the second control transistor while the first light emitting diode (LD1) emits light (Paragraphs [0079]-[0080] describes current flow from a power source VDD through LD1 and LD2 under control via T3 and voltage of N1. Paragraph [0086] describes a bypass wherein the current from LD1 bypasses LD2 via T2.).
Regarding claim 5, Kang and Leshniak discloses the display device according to claim 2, wherein the first control transistor (Leshniak: 104a) is turned on and the second control transistor (T2) is turned off while the second light emitting diode emits light (In view of the combination, function of a bypass transistor 104a and T2 it is inherent that 104a must be turned on in order to bypass LD1 and enable inspection of LD2 during light emission.).
Regarding claim 6, Kang discloses the display device according to claim 5, wherein a driving current flows from the first control transistor to the second light emitting diode while the second light emitting diode emits light (Paragraphs [0079]-[0080] describes current flow from a power source VDD through LD1 and LD2 under control via T3 and voltage of N1. Paragraph [0086] describes a bypass wherein the current from LD1 bypasses LD2 via T2. It is inherent in bypassing LD1 the current would flow through 104a (Leshniak) before reaching LD2 to emit light in the same manner as described in paragraph [0086].).
Allowable Subject Matter
5. Claims 7-12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 7, Kang discloses the display device according to claim 2, further comprising:
a gate driver (Figure 1 reference scan driver 200.) that is electrically connected (SL and CL) to the display panel (100), the gate driver configured to output a first scan signal (Figures 1 and 3 SLi), the first control signal (Leshniak control signal for 104a in the same manner as second control signal CCLi.), and the second control signal (CCLi) to the plurality of sub pixels (PX 10).
Kang does not specifically disclose wherein the gate driver (200) includes:
a plurality of first stages that generate the first scan signal; and
a plurality of control signal generating circuits each of which is connected to an output terminal of a corresponding one of the plurality of first stages and generates the first control signal and the second control signal to output the first control signal and the second control signal to a first control line and a second control line.
Kim et al. (US Patent Application Publication 2023/0169926) discloses wherein a gate driver (Figures 1, 4, and 6) includes:
a plurality of first stages (Figure 4 ST1-STn) that generate the first scan signal (Figures 4 and 6 reference output of SC.); and
a plurality of control signal generating circuits (Figure 6 139+137) each of which is corresponding to an output terminal (OUT1) of a corresponding one of the plurality of first stages (STn) and generates the first control signal (CR) and the second control signal (SS) to output the first control signal and the second control signal to a first control line (OUT3) and a second control line (OUT2).
However, Kim does not specifically disclose a plurality of control signal generating circuits each of which is connected to an output terminal of a corresponding one of the plurality of first stages and generates the first control signal and the second control signal to output the first control signal and the second control signal to a first control line and a second control line.
The outputs of OUT2 and OUT3 are generated without connection to OUT1.
Response to Arguments
6. Applicant's arguments filed 12/2/2025 have been fully and relate towards newly amended subject matter. Please refer to the above office action introducing newly cited art Liao utilized in combination to reject the subject matter. Liao was cited on the PTO-892 filed 9/24/2025. This action is final necessitated by amendment.
Conclusion
7. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER E LEIBY whose telephone number is (571)270-3142. The examiner can normally be reached 11-7.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amr Awad can be reached at 571-272-7764. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/CHRISTOPHER E LEIBY/ Primary Examiner, Art Unit 2621