DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Election/Restrictions
Claims 3-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 29 December 2025.
Applicant’s election without traverse of Species I, corresponding to originally filed Claims 1 and 2, in the reply filed on 29 December 2025 is acknowledged.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wang (US 2013 / 0271357).
As pertaining to Claim 1, Wang discloses (see Fig. 4 and Fig. 5) an electronic device (i.e., a display device) comprising:
a display panel (see (201)) comprising a plurality of pixels (410) arranged in a matrix;
a first main gate line (i.e., a first (441)) extending in a first direction (i.e., a horizontal direction) and configured to be electrically connectible to a first pixel (i.e., see a first, second, and third (410) in a first row) among the plurality of pixels (410);
a second main gate line (i.e., a second (441)) extending in the first direction (i.e., the horizontal direction) and configured to be electrically connectible to a second pixel (i.e., see a first, second, and third (410) in a second row) among the plurality of pixels (410), the second pixel (i.e., the first, second, and third (410) in the second row) being adjacent to the first pixel (i.e., the first, second, and third (410) in the first row) along a second direction (i.e., a vertical direction) intersecting the first direction (i.e., the horizontal direction);
a first main source line (i.e., a first (451) corresponding to a second (450) from the left) extending in the second direction (i.e., the vertical direction) and configured to be electrically connectible to the first pixel (i.e., the first, second, and third (410) in the first row);
a second main source line (i.e., a second (451) corresponding to a third (450) from the left) extending in the second direction (i.e., the vertical direction) and configured to be electrically connectible to a third pixel (i.e., see a fourth, fifth, and sixth (410) adjacent to the first pixel in the first row) among the plurality of pixels (410), the third pixel (i.e., the fourth, fifth, and sixth (410) adjacent to the first pixel in the first row) being adjacent to the first pixel (i.e., the first, second, and third (410) in the first row) in the first direction (i.e., the horizontal direction);
a switching circuit (i.e., see (440, 450) in Fig. 4 corresponding to (540, 550) in Fig. 5) connected to one of the first main gate line (i.e., a first (441)) or the first main source line (i.e., a first (451) corresponding to a second (450) from the left) and configured to selectively connect the first main gate line (i.e., a first (441)) to a first sub-pixel (i.e., a third (410)) included in the first pixel (i.e., the first, second, and third (410) in the first row) or a second sub-pixel (i.e., a third (410)) included in the second pixel (i.e., the first, second, and third (410) in the second row), or to selectively connect the first main source line (i.e., a first (451) corresponding to a second (450) from the left) to the first sub-pixel (i.e., the third (410) in the first row) or a third sub-pixel (i.e., a fourth (410)) in the third pixel (i.e., see the fourth, fifth, and sixth (410) adjacent to the first pixel in the first row); and
a display driving circuit (420, 430, 547) electrically connected to the display panel (see (210)) and configured to drive the display panel (see Page 7 through Page 8, Para. [0030]-[0031], [0033]-[0036], [0043]-[0045], and [0052]-[0054]).
As pertaining to Claim 2, Wang discloses (see Fig. 4 and Fig. 5) a first transistor array (see (413)) electrically connected to the first main gate line (i.e., a first (441)) and the first main source line (i.e., a first (451) corresponding to a second (450) from the left) and configured to drive the first sub-pixel (i.e., the third (410) in the first row),
wherein the switching circuit (i.e., see (440, 450) in Fig. 4 corresponding to (540, 550) in Fig. 5) is connected between the first transistor array (see (413)) and the first main gate line (i.e., a first (441)) or the first main source line (i.e., a first (451) corresponding to a second (450) from the left; see Page 7, Para. [0033]-[0036]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
A number of references not relied upon in the above rejections disclose display panels that are pertinent to the claimed invention. In particular, Xiong (US 2024 / 0386816) at least at Figure 2, Jeong et al. (US 12,014,690) at least at Figure 7, Huang (US 2023 / 0005442) at least at Figure 2, Kim et al. (US 2018 / 0342217) at least at Figure 10, Kim (US 2017 / 0076665) at least at Figure 2, Zhou et al. (US 2017 / 0061872) at least at Figure 10, Shi (US 2012 / 0086682) at least at Figure 1, and Hu (US 2006 / 0007195) at least at Figure 1.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JASON M MANDEVILLE whose telephone number is (571)270-3136. The examiner can normally be reached Mon - Fri 7:30AM-4:00PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chanh Nguyen can be reached at 571-272-7772. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/JASON M MANDEVILLE/Primary Examiner, Art Unit 2623