DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Election/Restrictions
Claims 3-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 29 December 2025.
Applicant’s election without traverse of Species I, corresponding to originally filed Claims 1 and 2, in the reply filed on 29 December 2025 is acknowledged.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2 are rejected under 35 U.S.C. 103 as being unpatentable over Wang (US 2013 / 0271357) in view of Li et al. (hereinafter “Li” US 2013 / 0127796).
As pertaining to Claim 1, Wang discloses (see Fig. 4 and Fig. 5) an electronic device (i.e., a display device) comprising:
a display panel (see (201)) comprising a plurality of pixels (410) arranged in a matrix;
a first main gate line (i.e., a first (441)) extending in a first direction (i.e., a horizontal direction) and configured to be electrically connectible to a first pixel (i.e., see a first, second, and third (410) in a first row) among the plurality of pixels (410);
a second main gate line (i.e., a second (441)) extending in the first direction (i.e., the horizontal direction) and configured to be electrically connectible to a second pixel (i.e., see a first, second, and third (410) in a second row) among the plurality of pixels (410), the second pixel (i.e., the first, second, and third (410) in the second row) being adjacent to the first pixel (i.e., the first, second, and third (410) in the first row) along a second direction (i.e., a vertical direction) intersecting the first direction (i.e., the horizontal direction);
a first main source line (i.e., a first (451) corresponding to a second (450) from the left) extending in the second direction (i.e., the vertical direction) and configured to be electrically connectible to the first pixel (i.e., the first, second, and third (410) in the first row);
a second main source line (i.e., a second (451) corresponding to a third (450) from the left) extending in the second direction (i.e., the vertical direction) and configured to be electrically connectible to a third pixel (i.e., see a fourth, fifth, and sixth (410) adjacent to the first pixel in the first row) among the plurality of pixels (410), the third pixel (i.e., the fourth, fifth, and sixth (410) adjacent to the first pixel in the first row) being adjacent to the first pixel (i.e., the first, second, and third (410) in the first row) in the first direction (i.e., the horizontal direction);
a switching circuit (i.e., see (440, 450) in Fig. 4 corresponding to (540, 550) in Fig. 5) connected to one of the first main gate line (i.e., a first (441)) or the first main source line (i.e., a first (451) corresponding to a second (450) from the left) and configured to selectively connect the first main gate line (i.e., a first (441)) to a first sub-pixel (i.e., a third (410)) included in the first pixel (i.e., the first, second, and third (410) in the first row) or a second sub-pixel (i.e., a third (410)) included in the second pixel (i.e., the first, second, and third (410) in the second row), or to selectively connect the first main source line (i.e., a first (451) corresponding to a second (450) from the left) to the first sub-pixel (i.e., the third (410) in the first row) or a third sub-pixel (i.e., a fourth (410)) in the third pixel (i.e., see the fourth, fifth, and sixth (410) adjacent to the first pixel in the first row); and
a display driving circuit (420, 430, 547) electrically connected to the display panel (see (210)) and configured to drive the display panel,
wherein the display driving circuit (420, 430, 547) is configured to:
control the switching circuit (again, see (440, 450) in Fig. 4 corresponding to (540, 550) in Fig. 5) to connect the first main gate line (i.e., a first (441)) or the first main source line (i.e., a first (451)) to a first pixel (410) to drive the sub-pixel (410), and
control the switching circuit (again, see (440, 450) in Fig. 4 corresponding to (540, 550) in Fig. 5) to connect the first main gate line (i.e., a first (441)) to a second pixel (410) to drive the second pixel (410), or to connect the first main source line (i.e., a first (451)) to a third pixel (410) to drive the third pixel (410; see Page 7 through Page 8, Para. [0030]-[0031], [0033]-[0036], [0043]-[0045], and [0052]-[0054]).
Wang does not explicitly disclose that each of the plurality of pixels (410) includes a plurality of sub-pixels configured to emit different colors from each other to collectively represent a color of the corresponding pixel. However, full-color display panels are well-known in the art.
In fact, in the same field of endeavor, Li discloses (see Fig. 2) a display panel (200) comprising a switching circuit (206), analogous to the switching circuit portion (450) disclosed by Wang, for selectively connecting a main line (208d1) to pixels (204) in the display panel (200; see Page 2, Para. [0025]-[0027]), wherein each of the plurality of pixels (204) includes a plurality of sub-pixels (R, G, B) configured to emit different colors (i.e., red, green, and blue) from each other to collectively represent a color of the corresponding pixel (see Page 2, Para. [0026]). It is a goal of Li to provide a means for reducing a number of components needed for the driving circuits of a display panel, through the implementation of a switching circuit connected to main lines of the display panel, to thereby reduce the manufacturing cost of the display panel (see Page 1, Para. [0001], [0005], and [0016]). This is likewise a goal of Wang (see Page 1, Para. [0008] of Wang). Further, Li discloses that which is implicit in the teachings of Wang and was well-known in the art before the effective filing date of the claimed invention, namely that each of the plurality of pixels (410) of Wang includes a plurality of sub-pixels configured to emit different colors from each other to collectively represent a color of the corresponding pixel in order to implement a full-color display.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Wang with the teachings of Li, such that each of the plurality of pixels (410) includes a plurality of sub-pixels configured to emit different colors from each other to collectively represent a color of the corresponding pixel, in order to provide a full-color display panel in which a number of components needed for the driving circuits of the display panel, as well as the manufacturing cost of the display panel, are reduced.
As pertaining to Claim 2, Wang discloses (see Fig. 4 and Fig. 5) a first transistor array (see (413)) electrically connected to the first main gate line (i.e., a first (441)) and the first main source line (i.e., a first (451) corresponding to a second (450) from the left) and configured to drive the first sub-pixel (i.e., the third (410) in the first row),
wherein the switching circuit (i.e., see (440, 450) in Fig. 4 corresponding to (540, 550) in Fig. 5) is connected between the first transistor array (see (413)) and the first main gate line (i.e., a first (441)) or the first main source line (i.e., a first (451) corresponding to a second (450) from the left; see Page 7, Para. [0033]-[0036]).
Response to Arguments
Applicant’s arguments with respect to Claims 1-2 have been considered but are moot because the new ground of rejection does not rely on a combination of references applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. The applicant has argued that none of the references relied upon by the examiner in the prior Office Action, namely Wang, teach or fairly suggest the newly claimed “sub-pixels” that are “configured to emit different colors from each other to collectively represent a color of the corresponding pixel” (see Remarks at Pages 13 through 15). The examiner respectfully points out that full-color displays utilizing sub-pixels to “collectively represent a color of the corresponding pixel” are well-known in the art. Further, respectfully, the applicant’s argument is moot in so much as the combined teachings of Wang and Li, as newly relied upon in the above rejections, clearly suggest all of the features of Claims 1-2 as current presented.
Therefore, the rejection of Claims 1-2 is maintained.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
A number of references not relied upon in the above rejections disclose display panels that are pertinent to the claimed invention. In particular, Xiong (US 2024 / 0386816) at least at Figure 2, Jeong et al. (US 12,014,690) at least at Figure 7, Huang (US 2023 / 0005442) at least at Figure 2, Kim et al. (US 2018 / 0342217) at least at Figure 10, Kim (US 2017 / 0076665) at least at Figure 2, Zhou et al. (US 2017 / 0061872) at least at Figure 10, Shi (US 2012 / 0086682) at least at Figure 1, and Hu (US 2006 / 0007195) at least at Figure 1.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JASON M MANDEVILLE whose telephone number is (571)270-3136. The examiner can normally be reached Mon - Fri 7:30AM-4:00PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chanh Nguyen can be reached at 571-272-7772. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JASON M MANDEVILLE/Primary Examiner, Art Unit 2623
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