DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-6, 9, and 13-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Albinet (US 2014/0266445), in view of Morzano et al. (US 6,392,453).
Figure 3 of Albinet has been annotated and reproduced below for discussion in the rejection.
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In regard to Claim 1:
Albinet discloses, in Figure 3, an operational amplifier comprising: an input stage (200A, 200B), the input stage comprising: a first inverter (200A) and a second inverter (200B) coupled together and configured to operate in a differential fashion (INM, INP are inputs to 200A, 200B); and an output stage (302), the output stage comprising: a third inverter (304) and a fourth inverter (306) coupled together, the third inverter (304) and the fourth inverter (306) selectively coupled to a supply voltage (AVDD) via a third switch (308, 310) and selectively coupled to a ground (AVSS) via a fourth switch (312, 314); a first capacitive coupling (320) configured to couple the third inverter (304) to a first output (OUTP1) of the input stage (200A); and a second capacitive coupling (322) configured to couple the fourth inverter (306) to a second output (OUTM1) of the input stage (200B).
Albinet does not disclose a first common-tail transistor selectively coupled to the first inverter and the second inverter via a first switch, the first common-tail transistor configured to define a biasing current; and a second common-tail transistor selectively coupled to the first inverter and the second inverter via a second switch.
Morzano discloses, in Figure 4, a first common-tail transistor (8) selectively coupled to the first inverter (30) and the second inverter (32) via a first switch (5), the first common-tail transistor configured to define a biasing current (Column 3: lines 62-66); and a second common-tail transistor (26) selectively coupled to the first inverter (30) and the second inverter (32) via a second switch (11).
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the common-tail transistors taught by Morzano with the differential amplifier taught by Albinet, since all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination yielded nothing more than predictable results to one of ordinary skill in the art. (KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385).
In regard to Claim 2:
Albinet further discloses, in Figure 3, the operational amplifier of claim 1 wherein:
the first inverter (200A) comprises a first PMOS transistor (201) and a first NMOS transistor (202) coupled together via a drain terminal of the first PMOS transistor and a drain terminal of the first NMOS transistor (the drains of 201 and 202 are coupled together); and
the second inverter (200B) comprises a second PMOS transistor (203) and a second NMOS transistor (204) coupled together via a drain terminal of the second PMOS transistor and a drain terminal of the second NMOS transistor (the drains of 203 and 204 are coupled together).
In regard to Claim 3:
Albinet further discloses, in Figure 3, the operational amplifier of claim 2 wherein:
the first PMOS transistor (201) and the second PMOS transistor (203) are coupled together via a source terminal of the first PMOS transistor and a source terminal of the second PMOS transistor (the sources of 201 and 203 are coupled together); and
the first NMOS transistor (202) and the second NMOS transistor (204) are coupled together via a source terminal of the first NMOS transistor and a source terminal of the second NMOS transistor (the source terminals of 202 and 204 are coupled together).
In regard to Claim 4:
Albinet further discloses, in Figure 3, the operational amplifier of claim 1 wherein:
the third inverter (304) comprises a third PMOS transistor (304p) and a third NMOS transistor (304n) coupled together via a drain terminal of the third PMOS transistor and a drain terminal of the third NMOS transistor (the drains of 304p and 304n are coupled together); and
the fourth inverter (306) comprises a fourth PMOS transistor (306p) and a fourth NMOS transistor (306n) coupled together via a drain terminal of the fourth PMOS transistor and a drain terminal of the fourth NMOS transistor (the drains of 306p and 306n are coupled together).
In regard to Claim 5:
Albinet further discloses, in Figure 3, the operational amplifier of claim 4 wherein:
the third PMOS transistor (304p) and the fourth PMOS transistor (306p) are coupled together via a source terminal of the third PMOS transistor and a source terminal of the fourth PMOS transistor (the sources of 304p and 306p are coupled together); and
the third NMOS transistor (304n) and the fourth NMOS transistor (306n) are coupled together via a source terminal of the third NMOS transistor and a source terminal of the fourth NMOS transistor (the sources of 304n and 306n are coupled together).
In regard to Claim 6:
Albinet further discloses, in Figure 3, the operational amplifier of claim 5 wherein:
a gate terminal of the third PMOS transistor (304p gate) and a gate terminal of the third NMOS transistor (304n gate) are coupled to the first output (OUTP1) of the input stage (200A) via the first capacitive coupling (320); and
a gate terminal of the fourth PMOS transistor (306p gate) and a gate terminal of the fourth NMOS transistor (306n gate) are coupled to the second output (OUTM1) of the input stage (200B) via the second capacitive coupling (322).
In regard to Claim 9:
Morzano further discloses, in Figure 3, the operational amplifier of claim 1 further comprising: a biasing current circuit (24) coupled to the first common-tail transistor (5).
In regard to Claim 13:
Albinet discloses, in Figure 3, an operational amplifier comprising: an input stage (200A, 200B), the input stage comprising: a first inverter (200A) and a second inverter (200B) coupled together and configured to operate in a differential fashion (INM, INP are inputs to 200A, 200B); and an output stage (302), the output stage comprising: a third inverter (304) and a fourth inverter (306) coupled together; a first capacitive coupling (320) configured to couple the third inverter (304) to a first output (OUTP1) of the input stage (200A); and a second capacitive coupling (322) configured to couple the fourth inverter (306) to a second output (OUTM1) of the input stage (200B).
Albinet does not dislose a first common-tail transistor coupled to the first inverter and the second inverter, the first common-tail transistor configured to define a biasing current; and a second common-tail transistor coupled to the first inverter and the second inverter.
Morzano discloses, in Figure 4, a first common-tail transistor (8) coupled to the first inverter (30) and the second inverter (32), the first common-tail transistor configured to define a biasing current (Column 3: lines 62-66); and a second common-tail transistor (26) coupled to the first inverter (30) and the second inverter (32).
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the common-tail transistors taught by Morzano with the differential amplifier taught by Albinet, since all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination yielded nothing more than predictable results to one of ordinary skill in the art. (KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385).
In regard to Claim 14:
Albinet further discloses, in Figure 3, the operational amplifier of claim 13 wherein:
the first inverter (200A) comprises a first PMOS transistor (201) and a first NMOS transistor (202) coupled together via a drain terminal of the first PMOS transistor and a drain terminal of the first NMOS transistor (the drains of 201 and 202 are coupled together); and
the second inverter (200B) comprises a second PMOS transistor (203) and a second NMOS transistor (204) coupled together via a drain terminal of the second PMOS transistor and a drain terminal of the second NMOS transistor (the drains of 203 and 204 are coupled together).
In regard to Claim 15:
Albinet further discloses, in Figure 3, the operational amplifier of claim 14 wherein:
the first PMOS transistor (201) and the second PMOS transistor (203) are coupled together via a source terminal of the first PMOS transistor and a source terminal of the second PMOS transistor (the sources of 201 and 203 are coupled together); and
the first NMOS transistor (202) and the second NMOS transistor (204) are coupled together via a source terminal of the first NMOS transistor and a source terminal of the second NMOS transistor (the source terminals of 202 and 204 are coupled together).
In regard to Claim 16:
Albinet further discloses, in Figure 3, the operational amplifier of claim 13 wherein:
the third inverter (304) comprises a third PMOS transistor (304p) and a third NMOS transistor (304n) coupled together via a drain terminal of the third PMOS transistor and a drain terminal of the third NMOS transistor (the drains of 304p and 304n are coupled together); and
the fourth inverter (306) comprises a fourth PMOS transistor (306p) and a fourth NMOS transistor (306n) coupled together via a drain terminal of the fourth PMOS transistor and a drain terminal of the fourth NMOS transistor (the drains of 306p and 306n are coupled together).
In regard to Claim 17:
Albinet further discloses, in Figure 3, the operational amplifier of claim 16 wherein:
the third PMOS transistor (304p) and the fourth PMOS transistor (306p) are coupled together via a source terminal of the third PMOS transistor and a source terminal of the fourth PMOS transistor (the sources of 304p and 306p are coupled together); and
the third NMOS transistor (304n) and the fourth NMOS transistor (306n) are coupled together via a source terminal of the third NMOS transistor and a source terminal of the fourth NMOS transistor (the sources of 304n and 306n are coupled together).
In regard to Claim 18:
Albinet further discloses, in Figure 3, the operational amplifier of claim 17 wherein:
a gate terminal of the third PMOS transistor (304p gate) and a gate terminal of the third NMOS transistor (304n gate) are coupled to the first output (OUTP1) of the input stage (200A) via the first capacitive coupling (320); and
a gate terminal of the fourth PMOS transistor (306p gate) and a gate terminal of the fourth NMOS transistor (306n gate) are coupled to the second output (OUTM1) of the input stage (200B) via the second capacitive coupling (322).
In regard to Claim 19:
Morzano further discloses, in Figure 3, the operational amplifier of claim 1 further comprising: a biasing current circuit (24) coupled to the first common-tail transistor (5).
Claim(s) 7 and 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Albinet (US 2014/0266445) and Morzano et al. (US 6,392,453) as applied to claims 1-6, 9, and 13-19 above, and further in view of Yi et al. (US 2019/0190505).
In regard to Claim 7:
All of the claim limitations have been discussed with respect to Claim 1 above, except for wherein the first capacitive coupling comprises a first switched-capacitor circuit.
Yi discloses, in Figure 7, wherein the first capacitive coupling (capacitors coupled between INT1 and INT2) comprises a first switched-capacitor circuit (S1, C1).
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the switched capacitor circuit taught by Yi with the differential amplifier taught by Albinet and Morzano, since all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination yielded nothing more than predictable results to one of ordinary skill in the art. (KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385).
In regard to Claim 8:
All of the claim limitations have been discussed with respect to Claim 1 above, except for wherein the second capacitive coupling comprises a second switched-capacitor circuit.
Yi discloses, in Figure 7, wherein the second capacitive coupling (capacitors coupled between INT3 and INT4) comprises a second switched-capacitor circuit (S4, C4).
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the switched capacitor circuit taught by Yi with the differential amplifier taught by Albinet and Morzano, since all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination yielded nothing more than predictable results to one of ordinary skill in the art. (KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385).
Allowable Subject Matter
Claims 10-12 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Link et al. (US 2018/00337645) discloses a differential inverter amplifier that can include a plurality of load resistors and a plurality of diode-connected metal oxide semiconductor (MOS) clamps configured to limit output swing and minimize common mode disturbances.
Huang et al. (US 2013/0335145) discloses a transimpedance amplifier includes a first inverter having a first input node and a first output node. The first input node is configured to be coupled to an input signal. A second inverter has a second input node and a second output node. The second input node is configured to receive a reference voltage terminal. The first inverter and the second inverter are configured to provide a differential output voltage signal between the first output node and the second output node.
Kwon (US 2006/0139066) discloses a differential amplifier has a current source connected between a power source voltage terminal and a current source node. A current sink is connected between a current sink node and a ground terminal. The inverters each comprising series connected P-channel and N-channel transistors, are connected between the current source node and the current sink node, to receive differential input signal and output the inverted input signals to the output nodes.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to John W Poos whose telephone number is (571)270-5077. The examiner can normally be reached M-Th 8-5.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Han can be reached at 571-272-2078. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JOHN W POOS/Primary Examiner, Art Unit 2843
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