Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments filed March 19, 2026, with respect to the rejection(s) of claims 1 – 20 under 35 U.S.C. 102 have been fully considered but are not persuasive.
Applicant argues that Camp’s errors merely indicate that a program or erase operation would fail, and not whether it is successful, and further argues that the type of errors discussed in Camp is different from, and cannot be relied on to disclose an “erase status indication or a program status indication”. The Examiner respectfully disagrees. Although Camp does not use the same terminology of a “program status indication”, the access operations are program operations, and the status comprises a program status indication. As stated in paragraph 0003 of the Specification, in the context of storing information by the memory device to the memory cells, “program” and “write” are synonyms. Paragraphs 0056 – 0060 of Camp teach a write operation by the controller to the memory, and paragraph 0061 describes the write operation as programming of the physical page. Paragraph 0061 notes that the controller may check whether the programming completed correctly, and handles failure in the same manner as reads, which are described in paragraphs 0065 – 0071. Paragraph 0065 determines an error in the operation and paragraph 0066 updates the status. The status is an indication of whether the access completed correctly, i.e. it indicates whether an access operation for the block of memory cells is successful, the access operation comprising a program operation.
Additionally, although this does not affect the current rejection as the claims only require one of a program status or an erase status, in the interest of compact prosecution the Examiner respectfully notes that while Camp does not expressly anticipate an erase operation, it does suggest it. Camp paragraph 0040 teaches erase blocks and paragraphs 0053/0054 teach program/erase cycles.
A rejection of the claims clarified to address the applicant’s arguments is included below.
Claim Rejections - 35 USC § 102
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Regarding claim 1, Camp teaches a method, comprising:
operating in an error correction mode for one or more blocks of memory cells of a memory system (Paragraphs 0065/0066, ECC is used. The ECC operates on a page level, but as per paragraphs 0030, 0038 and 0069, the flash controller also manages memory at the block level);
monitoring, for a block of memory cells of the one or more blocks of memory cells and based on the error correction mode (Paragraph 0030, tracking information regarding the memory and blocks), a status associated with the block of memory cells (Paragraphs 0030 – 0032, the error metrics per block or page), wherein the status indicates whether an access operation for the block of memory cells is successful, the access operation comprising a program operation (Paragraph 0061, the access operation can be a write operation, which is “programming of the physical page”) or an erase operation, and wherein the status comprises an erase status indication or a program status indication (Paragraph 0061, the controller attempts to write to the page, and identifies whether the write completes correctly. Paragraph 0061 states that failures in writing can retire pages in a similar manner to reading, which is described in paragraphs 0065 – 0071. The controller updates the status in paragraph 0066, where it updates the error metrics with errors found for the page/block storing the page) and
storing information, based on the status associated with the block of memory cells, that indicates whether the block of memory cells is available for one or more subsequent access operations, wherein the information indicates whether the block of memory cells is included in a first group of blocks within the memory system that are available for the one or more subsequent access operations or a second group of blocks within the memory system that are not available for the one or more subsequent access operations (Paragraph 0030, the available block queue indicates the first group of blocks that are available for access operations. Paragraphs 0038 and 0069, the controller indicates the second group by marking the pages and blocks as retired from use).
Regarding claim 2, Camp teaches the method of claim 1, wherein the information comprises an indication that the block of memory cells is not available based on the status indicating that the access operation is unsuccessful (Paragraph 0066/0067, if the page is found to contain a data error, an indicator is stored marking it as retired. This updates the error metrics, which is information at the block level. This can lead to retirement at the block level as per paragraph 0069. See Fig. 12 block 1220).
Regarding claim 3, Camp teaches the method of claim 1, wherein the information comprises an indication that the block of memory cells is available based on the status indicating that the access operation is successful (Referring to Fig. 12, if there is no error in the test access at block 1206/1210, it completes without updating error metrics / negatively impacting health grade, and the block is not marked as retired. Paragraph 0051/0055, this can lead to the block being placed in the ABQ based on its health grade to indicate it is available.).
Regarding claim 4, Camp teaches the method of claim 1, further comprising:
operating the memory system in an idle mode (Paragraph 0052, the health grading can be performed in the background during idle times);
performing, while operating in the idle mode, one or more requalification operations (Paragraph 0053, determining the health grade of the block of memory, and may perform determination of error metrics; This can include the data correction in paragraph 0066 which updates the error metrics) on the block of memory cells based on the block of memory cells being included in the first group of blocks, wherein the block of memory cells is included in the first group of blocks based on the status indicating that the access operation for the block of memory cells is successful (Paragraph 0052, the list of blocks being iterated through may be a list of blocks holding memory that have been written to or are empty; i.e. are not retired), and wherein storing the information is further based on the one or more requalification operations (Paragraph 0053, the determination of error metrics may be the requalification operations).
Regarding claim 5, Camp teaches the method of claim 4, wherein the information indicates that the block of memory cells is available for the one or more subsequent access operations based on an error rate associated with the one or more requalification operations being less than or equal to a threshold error rate (Paragraph 0069, if the number of retired pages is below a threshold for a block, the block is not retired).
Regarding claim 6, Camp teaches the method of claim 4, wherein the information indicates that the block of memory cells is not available for the one or more subsequent access operations based on the one or more requalification operations being unsuccessful (Paragraph 0066/Fig. 12, the page is only potentially marked for retirement if the ECC correction failed to correct the error).
Regarding claim 7, Camp teaches the method of claim 4, wherein the information indicates that the block of memory cells is not available for the one or more subsequent access operations based on an error rate associated with the one or more requalification operations being greater than a threshold error rate (Paragraph 0069, if the number of retired pages is above a threshold for a block, the block is retired).
Regarding claim 8, Camp teaches the method of claim 4, further comprising:
storing first information that indicates that the block of memory cells is recoverable from an error condition based on the status indicating that the access operation is successful (Paragraph 0066 / 0068, if the number of error bits is correctable, the block is not marked as retired), wherein the first information further indicates that the block is included in the first group of blocks (The block is not marked as retired. Paragraphs 0051 / 0055, the block may be placed in the available block queue based on its health score).
Regarding claim 9, Camp teaches the method of claim 4, wherein the one or more requalification operations comprise one or more erase operations (Paragraph 0057, erasing invalidated pages), one or more program operations, one or more read operations (Fig. 12), or any combination thereof to refresh the block of memory cells for the one or more subsequent access operations (Paragraph 0030, erasing places the block in the erased block list, and functional blocks are placed in the available block queues for future access).
Regarding claim 10, Camp teaches the method of claim 1, wherein storing the information comprises:
storing, in a set of metadata, first metadata comprising the information and a first identifier of the block of memory cells (Paragraph 0038, on a page level, the information is stored as a table; Paragraph 0030 – 0033, on a block level, data structures comprising the information and identifying whether the block belongs in a given category), and second metadata comprising second identifiers of one or more second blocks of memory cells from among the one or more blocks of memory cells of the memory system and second information that indicates whether the one or more second blocks of memory cells are available for subsequent access operations (Paragraphs 0030 – 0033, the ABQs indicating the health of the blocks. Alternatively the other structures or error metrics structures indicate whether the block is retired or not).
Regarding claim 11, Camp teaches the method of claim 10, wherein the first identifier comprises an address associated with the block of memory cells (Paragraphs 0029, 0031, 0039 – 0041, 0043 – 0045 the flash controller handles address translation, and can store the logical and physical addresses of memory).
Regarding claim 12, Camp teaches the method of claim 1, wherein the error correction mode is based on a failed read operation for the one or more blocks of memory cells (Paragraph 0066, the ECC attempts to correct a data error in the read).
Regarding claim 13, Camp teaches the method of claim 1, wherein the error correction mode comprises a redundant array of independent not-and (RAIN) operations (Paragraph 0028, the memory may be NAND memory; Paragraph 0044, the ECC data protection of the memory is in a RAID 5 scheme).
Regarding claim 14, Camp teaches the method of claim 1, wherein the status comprises an erase status failure indication or a program status failure indication (Paragraph 0061, a determination for whether or not the programming of the physical page completed correctly. If the write is unsuccessful, the flash controller can retire a physical page in the same way as a read operation. Paragraph 0066 teaches that such a read operation updates the error metrics with the errors, constituting a program status failure indication).
Regarding claim 15, Camp teaches a non-transitory computer-readable medium storing code (Paragraphs 0018 and 0077).
Claim 15 otherwise recites similar language to claim 1, and is similarly rejected.
Claim 16 recites similar language to claim 2, and is similarly rejected.
Claim 17 recites similar language to claim 3, and is similarly rejected.
Claim 18 recites similar language to claim 4, and is similarly rejected.
Claim 19 recites similar language to claim 5, and is similarly rejected.
Regarding claim 20, Camp teaches an apparatus, comprising: a controller associated with a memory device, wherein the controller is configured to cause the apparatus to perform operations (Abstract).
Claim 20 otherwise recites similar language to claim 1, and is similarly rejected.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Intel (Interfacing the Intel Flash 28F001BX-T to Your 186 Based System) teaches that erase and program statuses have been known in the art for a significant amount of time.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRYAN PAI SONG HUANG whose telephone number is (571)272-0510. The examiner can normally be reached Monday - Friday 11:30 AM - 8:30 PM.
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/B.P.H./Examiner, Art Unit 2114
/ASHISH THOMAS/Supervisory Patent Examiner, Art Unit 2114
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