DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 1-8 and 9 are objected to because of the following informalities:
“the interpose” in line 7 of claim 1 should read as “the interposer”.
“Claim1” in line 1 of claim 2 should read as “claim 1”.
“a second optical electrical engine” in line 8 of claim 2 should read as “the second optical electrical engine”.
“Claim1” in line 1 of claim 3 should read as “claim 1”.
“Claim 1” in line 1 of claim 4 should read as “claim 1”.
“Claim 4” in line 1 of claim 5 should read as “claim 4”.
“Claim 1” in line 1 of claim 6 should read as “claim 1”.
“Claim 6” in line 1 of claim 7 should read as “claim 6”.
“the ASIC switch” in lines 4-5 of claim 6 should read as “an ASIC switch”.
“Claim 8” in line 1 of claim 9 should read as “claim 8”.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 8 and 10 are rejected under 35 U.S.C. 102(a)(1) and 35 U.S.C. 102(a)(2) as being anticipated by Meade (US 2021/0258078).
Regarding claim 8, Meade teaches a computing system (Fig. 2C, Computing system 200C) comprising: an interposer (Fig. 2C, Interposer 201C), a first processing unit disposed on the interposer (Fig. 2C, SoC 203 on interposer 201C); a first optical electrical switch connected to the first processing unit (Fig. 2C, TeraPHY fanout circuit 207C is an optical electrical switch (see Figure 10, switch 400) that is connected to the first processing unit 203 via optical interconnection 115I/H/G and 103C; Paragraph 0050, optical interface of the MIPO I/O chiplet 103C is optically connected through optical fiber arrays 115G, 115H, 115I to an optical interface of an optical fanout chiplet 207C… Paragraph 0088, each of the optical fanout chiplets 111, 207, 207A, 207B, 207C, 207D, as shown in FIGS. 1 through 2D, is substituted for by a combination of a TeraPHY chiplet and an electrical fanout chiplet… Paragraph 0103, CXL Hub/FO (fanout) chip 501 is an electrical fanout chip); a second optical electrical switch connected to a first memory component (Fig. 2C, TeraPHY fanout circuit 207A (i.e. second optical electrical switch) is coupled to first HBM 113 (i.e. first memory component)); and a third optical electrical switch connected to a second memory component (Fig. 2C, TeraPHY fanout circuit 207B (i.e. third optical electrical switch) is coupled to second HBM 113 (i.e. second memory component)).
Regarding claim 10, Meade teaches a method of enlarging the capacity of a computer system (Fig. 2C, System 200C) comprising the steps of: transmitting a first electrical signal from a first memory component to a first processing unit (Fig. 2C, HBM 113 of 201C transmits signal to GPU 203; Paragraph 0050, SoC MCP 201C also has the HBM interface 107D of the GPU 203 connected to an HBM stack 113 onboard the SoC MCP 201C… Paragraph 0037, MIPO I/O chiplets provide for translation/conversion of data communication from the electrical domain to the optical domain, and vice-versa); transmitting the first electrical signal from the first processing unit to a first optical electrical engine (Fig. 2C, GPU 203 transmits electrical signals to TeraPHY chiplet 103A that converts electrical signals to optical signals; Paragraph 0049, SoC MCP 201C includes the MIPO I/O chiplet 103A optically connected to the HBM card 205A through optical fiber arrays 115A, 115B, 115C); converting the first electrical signal to a first optical signal (Fig. 2C, TeraPHY chiplet 103A converts electrical signal to optical signal; Paragraph 0042, MIPO I/O chiplet 103A-103D converts digital data received in the electrical domain through the corresponding HBM interface 107A-107D into an optical data stream (into a stream of modulated light that conveys the digital data) and transmits the optical data stream over an optical connection provided by optical fiber arrays 115A, 115B, 115C); transmitting the first optical signal to a second optical electrical engine (Fig. 2C, Optical signals are transmitted over optical fibers 115A/B/C); converting the first optical signal into a second electrical signal (Fig. 2C, TeraPHY chiplet 207A (see Fig. 10, 401 which is synonymous with Fig. 1, 111) converts optical signal to electrical signal; Paragraph 0053, Each of the optical fanout chiplets 207A, 207B, 207C, and 207D is like the optical fanout chiplet 111… Paragraph 0043, optical fanout chiplet 111 converts digital data received in optical form (e.g., as streams of modulated light) from the SoC MCP 101 into corresponding electrical signals); transmitting the second electrical signal to a second processing unit (Fig. 10, TeraPHY chiplet 401 transmits electrical signal to electrical fanout chiplet 403); and transmitting the second electrical signal to a second memory component (Fig. 10, Electrical fanout chiplet 403 (i.e. synonymous with Fig. 1, 111) transmits electrical signals to HBM 113; Paragraph 0043, optical fanout chiplet 111 then directs the electrical signals conveying the digital data received that was received in optical form to one or more of the HBM stacks 113).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 2 are rejected under 35 U.S.C. 103 as being unpatentable over Meade (US 2021/0258078) in view of Lazovsky (US 2023/0297237).
Regarding claim 1, Meade teaches a computing system (Fig. 2C, Computing system 200C; Paragraph 0049, MIPO I/O-enabled HBM extender system 200C) comprising: an interposer (Fig. 2A, 201C is an interposer), a first processing unit disposed on the interposer (Fig. 2C, GPU 203); a second processing unit (Fig. 2C, TeraPHY 207A contains an electrical fanout chiplet (See Fig. 10, 403) that is a CXL processing unit (See Fig. 14, 501); Paragraph 0049, optical fanout chiplet 207A… Paragraph 0088, each of the optical fanout chiplets 111, 207, 207A, 207B, 207C, 207D, as shown in FIGS. 1 through 2D, is substituted for by a combination of a TeraPHY chiplet and an electrical fanout chiplet… Paragraph 0103, CXL Hub/FO (fanout) chip 501 is an electrical fanout chip); a first high bandwidth memory unit, disposed on the interposer (Fig. 2C, HBM 113 on interposer 201C), and connected to the first processing unit (Paragraph 0050, SoC MCP 201C also has the HBM interface 107D of the GPU 203 connected to an HBM stack 113 onboard the SoC MCP 201C); a second high bandwidth memory unit and coupled to the second processing unit (Fig. 2C, HBM 113 on 205A is coupled to TeraPHY chiplet 207A containing the CXL electrical fanout hub (i.e. second processing unit)); a first optical electrical engine connected to the first processing unit (Fig. 2C, 103A is a first optical electrical engine coupled to GPU 203 (i.e. first processing unit); Paragraph 0049, SoC MCP 201C includes the MIPO I/O chiplet 103A optically connected to the HBM card 205A through optical fiber arrays 115A, 115B, 115C); and a second optical electrical engine connected to second processing unit (Fig. 2C, TeraPHY chiplet 207A is an optical electrical engine (see Fig. 10, 401; i.e. second optical electrical engine) coupled to CXL electrical fanout chiplet (see Fig. 10, 403; i.e. second processing unit); Paragraph 0088, each of the optical fanout chiplets 111, 207, 207A, 207B, 207C, 207D, as shown in FIGS. 1 through 2D, is substituted for by a combination of a TeraPHY chiplet and an electrical fanout chiplet).
Meade does not teach the computing system comprising the second processing unit disposed on the interposer; the second high bandwidth memory unit, disposed on the interposer.
Lazovsky teaches the computing system comprising the second processing unit disposed on the interposer (Fig. 10, Processing elements are part of same interposer; Paragraph 0027, Groups of memory can surround a client chip on a single interposer, and several chips and memory can be integrated onto a single interposer… Paragraph 0028, FIG. 10, in one beneficial implementation, a balance can be achieved by overlaying two mesh networks—a memory mesh (1001) and a compute mesh (1002)); the second high bandwidth memory unit, disposed on the interposer (Fig. 10, HBM stacks 1003 are part of same interposer; Paragraph 0027, a set of point-to-point channels connect an HBM stack to one or more fabric interfaces located in the same or several chips).
Meade and Lazovsky are analogous arts because they are in the same field of endeavor of utilizing optical interconnects to transmit optical signals between high bandwidth memory stacks.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Meade’s computing system to incorporate the teachings of Lazovsky and include the second processing unit and second HBM unit onto the same interposer as the first processing unit and the first HBM unit.
One of ordinary skill in the art would be motivated to make the modifications in order to create higher-density chip designs that are power and thermal efficient, while providing higher bandwidth topologies (See Lazovsky: Paragraph 0027).
Regarding claim 2, Meade in view of Lazovsky teaches the computing system of claim 1. Meade teaches the computing system comprising wherein data is transmitted between the first processing unit and the second processing unit according to the method comprising the steps of: transmitting a first electrical signal from the first high bandwidth memory to the first processing unit (Fig. 2C, HBM 113 of 201C transmits signal to GPU 203; Paragraph 0050, SoC MCP 201C also has the HBM interface 107D of the GPU 203 connected to an HBM stack 113 onboard the SoC MCP 201C… Paragraph 0037, MIPO I/O chiplets provide for translation/conversion of data communication from the electrical domain to the optical domain, and vice-versa); transmitting the first electrical signal from the first processing unit to the first optical electrical engine (Fig. 2C, GPU 203 transmits electrical signals to TeraPHY chiplet 103A that converts electrical signals to optical signals; Paragraph 0049, SoC MCP 201C includes the MIPO I/O chiplet 103A optically connected to the HBM card 205A through optical fiber arrays 115A, 115B, 115C); converting the first electrical signal to a first optical signal (Fig. 2C, TeraPHY chiplet 103A converts electrical signal to optical signal; Paragraph 0042, MIPO I/O chiplet 103A-103D converts digital data received in the electrical domain through the corresponding HBM interface 107A-107D into an optical data stream (into a stream of modulated light that conveys the digital data) and transmits the optical data stream over an optical connection provided by optical fiber arrays 115A, 115B, 115C); transmitting the first optical signal to a second optical electrical engine (Fig. 2C, Optical signals are transmitted over optical fibers 115A/B/C); converting the first optical signal into a second electrical signal (Fig. 2C, TeraPHY chiplet 207A (see Fig. 10, 401 which is synonymous with Fig. 1, 111) converts optical signal to electrical signal; Paragraph 0053, Each of the optical fanout chiplets 207A, 207B, 207C, and 207D is like the optical fanout chiplet 111… Paragraph 0043, optical fanout chiplet 111 converts digital data received in optical form (e.g., as streams of modulated light) from the SoC MCP 101 into corresponding electrical signals); transmitting the second electrical signal to a second processing unit (Fig. 10, TeraPHY chiplet 401 transmits electrical signal to electrical fanout chiplet 403); and transmitting the second electrical signal to the second high bandwidth memory (Fig. 10, Electrical fanout chiplet 403 (i.e. synonymous with Fig. 1, 111) transmits electrical signals to HBM 113; Paragraph 0043, optical fanout chiplet 111 then directs the electrical signals conveying the digital data received that was received in optical form to one or more of the HBM stacks 113).
Claims 4-7 are rejected under 35 U.S.C. 103 as being unpatentable over Meade (US 2021/0258078) in view of Lazovsky (US 2023/0297237) and further in view of Dorta-Quinones (US 2023/0308188).
Regarding claim 4, Meade in view of Lazovsky teaches the computing system of claim 1. Meade teaches the computing system further comprising: a switch (Figs. 2C and 10, TeraPHY chiplet 207C containing CXL electrical fanout chiplet 403 shown in Figure 10); a third optical electrical engine disposed on the interposer (Fig. 2C, Third optical electrical engine 103C); a fourth optical electrical engine connected to the switch (Figs. 2C and 10, TeraPHY chiplet 207C); and a third high bandwidth memory (Fig. 2C, HBM 113 of 205C).
Lazovsky teaches the computing system further comprising: the switch (Figs. 9 and 10, Router 902 in Figure 9 and shown in Figure 10), optical electrical engine (Fig. 10. Photonic interface of 1003), and high bandwidth memory disposed on the interposer (Fig. 10, HBM 1003).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Meade’s computing system to incorporate the teachings of Lazovsky and include the second processing unit and second HBM unit onto the same interposer as the first processing unit and the first HBM unit.
One of ordinary skill in the art would be motivated to make the modifications in order to create higher-density chip designs that are power and thermal efficient, while providing higher bandwidth topologies (See Lazovsky: Paragraph 0027).
Neither Meade nor Lazovsky teaches the computing system further comprising an ASIC switch.
Dorta-Quinones teaches the computing system further comprising an ASIC switch (Fig. 2-8C, ASIC switch; Paragraph 0230, FIG. 2-8C illustrates a photonic interposer 20 hosting 16 ASICs with AIB interfaces. Each ASIC may be mounted on a respective tile of the photonic interposer).
Meade, Lazovsky, and Dorta-Quinones are analogous arts because they are in the same field of endeavor of routing optical signals along photonic interconnections in an HBM system.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Meade/Lazovsky’s computing system to incorporate the teachings of Dorta-Quinones and utilize an ASIC switch for the switch of Meade.
One of ordinary skill in the art would be motivated to make the modifications in order to enable high bandwidth communications with densely integrated chip designs and packaging (See Dorta-Quinones: Paragraphs 0227 and 0228).
Regarding claim 5, the combination of Meade/Lazovsky/Dorta-Quinones teaches the computing system of claim 4. Meade teaches the computing system comprising wherein data is transmitted between the first processing unit and the second processing unit according to the method comprising the steps: transmitting the first electrical signal from the first processing unit to the third optical electrical engine (Fig. 2C, GPU 203 transmits signals to third optical electrical engine 103C); converting the first electrical signal to a first optical signal (Fig. 2C, 103C converts electrical to optical signal; Paragraph 0050, optical interface of the MIPO I/O chiplet 103C is optically connected through optical fiber arrays 115G, 115H, 115I to an optical interface of an optical fanout chiplet 207C); transmitting the first optical signal to the fourth optical electrical engine (Fig. 2C, 103C to TeraPHY chiplet 207C); converting the first optical signal to a second electrical signal (Fig. 10, TeraPHY chiplet 401 converts optical signal to electrical signal); transmitting the second electrical signal to the switch (Fig. 10, CXL electrical fanout chiplet 403 receives the electrical signal); and transmitting the second electrical signal to third high bandwidth memory (Fig. 10, CXL electrical fanout chiplet transmits signals to third HBM 113).
Dorta-Quinones teaches the computing system further comprising an ASIC switch (Fig. 2-8C, ASIC switch; Paragraph 0230, FIG. 2-8C illustrates a photonic interposer 20 hosting 16 ASICs with AIB interfaces. Each ASIC may be mounted on a respective tile of the photonic interposer).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Meade/Lazovsky’s computing system to incorporate the teachings of Dorta-Quinones and utilize an ASIC switch for the switch of Meade.
One of ordinary skill in the art would be motivated to make the modifications in order to enable high bandwidth communications with densely integrated chip designs and packaging (See Dorta-Quinones: Paragraphs 0227 and 0228).
Regarding claim 6, Meade in view of Lazovsky teaches the computing system of claim 1. Meade teaches the computing system further comprising: an optical switch (Figs. 2C and 10, TeraPHY chiplet 207C contains chiplet 401 shown in Figure 10); a third optical electrical engine disposed on the interposer (Fig. 2C, Third optical electrical engine 103C); a fourth optical electrical engine (Figs. 2C and 10, TeraPHY chiplet 207C) connected to a switch (Figs. 2C and 10, TeraPHY chiplet 207C containing CXL electrical fanout chiplet 403 shown in Figure 10); and a third high bandwidth memory (Fig. 2C, HBM 113 of 205C).
Lazovsky teaches the computing system further comprising: the switch (Figs. 9 and 10, Router 902 in Figure 9 and shown in Figure 10), optical electrical engine (Fig. 10. Photonic interface of 1003), and high bandwidth memory disposed on the interposer (Fig. 10, HBM 1003).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Meade’s computing system to incorporate the teachings of Lazovsky and include the second processing unit and second HBM unit onto the same interposer as the first processing unit and the first HBM unit.
One of ordinary skill in the art would be motivated to make the modifications in order to create higher-density chip designs that are power and thermal efficient, while providing higher bandwidth topologies (See Lazovsky: Paragraph 0027).
Neither Meade nor Lazovsky teaches the computing system further comprising an ASIC switch.
Dorta-Quinones teaches the computing system further comprising an ASIC switch (Fig. 2-8C, ASIC switch; Paragraph 0230, FIG. 2-8C illustrates a photonic interposer 20 hosting 16 ASICs with AIB interfaces. Each ASIC may be mounted on a respective tile of the photonic interposer).
Meade, Lazovsky, and Dorta-Quinones are analogous arts because they are in the same field of endeavor of routing optical signals along photonic interconnections in an HBM system.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Meade/Lazovsky’s computing system to incorporate the teachings of Dorta-Quinones and utilize an ASIC switch for the switch of Meade.
One of ordinary skill in the art would be motivated to make the modifications in order to enable high bandwidth communications with densely integrated chip designs and packaging (See Dorta-Quinones: Paragraphs 0227 and 0228).
Regarding claim 7, the combination of Meade/Lazovsky/Dorta-Quinones teaches the computing system of claim 6. Meade teaches the computing system comprising wherein data is transmitted between the first processing unit and the second processing unit according to the method comprising the steps: transmitting the first electrical signal from the first processing unit to the third optical electrical engine (Fig. 2C, GPU 203 transmits signals to third optical electrical engine 103C); converting the first electrical signal to a first optical signal (Fig. 2C, 103C converts electrical to optical signal; Paragraph 0050, optical interface of the MIPO I/O chiplet 103C is optically connected through optical fiber arrays 115G, 115H, 115I to an optical interface of an optical fanout chiplet 207C); transmitting the first optical signal to the fourth optical electrical engine (Fig. 2C, 103C to TeraPHY chiplet 207C); converting the first optical signal to a second electrical signal (Fig. 10, TeraPHY chiplet 401 converts optical signal to electrical signal); transmitting the second electrical signal to the optical switch (Fig. 10, CXL electrical fanout chiplet 403 receives the electrical signal); and transmitting the second electrical signal to third high bandwidth memory (Fig. 10, CXL electrical fanout chiplet transmits signals to third HBM 113).
Allowable Subject Matter
Claims 3 and 9 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, and if the Claim Objections are overcome.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US PGPUB 2024/0036278 to Toma discloses an optical interconnect that transfers data from an HBM stack.
US PGPUB 2023/0343718 to Zhou discloses an interposer with a logic block and memory block that are coupled to another interposer with a separate memory block and logic block via optical interconnects.
US Patent 8,546,955 to Wu discloses a multi-stack memory die system coupled via an optical interconnect.
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/H.Z.W./Examiner, Art Unit 2184
/HENRY TSAI/Supervisory Patent Examiner, Art Unit 2184
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