DETAILED ACTION
This office action is in response to a Request for Continued Examination (RCE) filed 3/13/2026 for application 18/776,341 that claims priority to PRO 63/536,818 field 9/6/2023.
Claims 1, 6, 10, 15, and 19 have been amended. Claims 4-5, 13-14 have been cancelled. Claims 21-23 are new. Thus claims 1-3, 6-12, and 15-23 have been examined.
The IDS sent 3/23/2026 has been considered.
The objections and rejections from the prior correspondence that are not restated herein are withdrawn.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 3/13/2026 has been entered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6, 8-12, 15-20, and 22-23 are rejected under 35 U.S.C. 103 as being unpatentable over Ramalingam (RAMALINGAM US 2016/0283116 A1 published 9/29/2016 by Intel Corporation) and further in view of Navon (Navon et al., us 2020/0242037 A1) and Fischer (FISCHER et al., US 2018/0307598 A1).
Regarding claim 1, A system (Ramalingam [0002] discloses the embodiments are directed to a computing system)
comprising: a plurality of submission queues, (Ramalingam [0002] discloses the host presents requests to one or more storage command submission queues.) each submission queue of the plurality of submission queues being associated with a corresponding submission queue identifier, (Ramalingam Fig. 2 and supporting para [0057] discloses each pending command may contain a submission Queue ID that identifies the source of the particular submission queue entry of each pending command, thus each submission queue has an associated qid. Ramalingam Fig. 2 discloses that these commands may be read, write, or other storage commands issued by the associated processor node to the SSD.) each submission queue identifier being associated with at least one hardware processor core of a host system; (Ramalingam [0055] discloses the write commands were received from multiple submission queues 124 a, 124, . . . 124 n from multiple processor nodes 104 a, 104 b . . . 104 n. See also Ramalingam [0002] that each processor node may contain a central processing unit that is an example of a hardware processor core. Thus each submission queue is associated with a queue identifier and is associated with a processor core.)
a memory device; and (Ramalingam Fig. 1 and para [0023] discloses solid state drive 106 that is an example of a memory device containing Nonvolatile Storage 120.)
a processing device, operatively coupled to the memory device, configured to perform operations comprising: (Ramalingam [0024] discloses Block Storage Controller 110 within Solid State Drive 106, where the SSD 106 is an example of a processing devices coupled to the memory device (nonvolatile Storage 120).)
receiving a set of command requests from a host system, (Ramalingam [0026] discloses computing system 100 that may be a person computer, a mainframe, a telephony deice, a smart phone, etc. that sends read, write or other storage commands. Ramalingam [0027] discloses the commands received from the host are placed in a Pending Write Command Queue 132 where the format of the Pending Write Command Queue 132 is detailed in Fig. 2 and paras [0027]-[0028].) each individual command request in the set of command requests comprising an individual submission queue identifier and being stored to an individual submission queue of a plurality of submission queues associated with the individual submission queue identifier; (Ramalingam Fig. 2 and paras [0027], and [0056]-[0058] discloses commands received from the host and placed in the Pending Write Command Queue 132 that is a submission queue for commands to the SSD and contains a Submission Queue ID that identifies one of the multiple submission queues 124 a, 124, . .. 124 n, thus each entry in queue 132 is a command request comprising an individual queue identifier and was stored to an individual submission queue of the multiple submission queues.)
obtaining, from a select submission queue of the plurality of submission queues, a select write request that comprises a select memory address, the select submission queue being associated with a select submission queue identifier; (Ramalingam [0027] discloses the block storage controller 110 receives write commands from the various submission queues 124a to 124n that contain a LBA, the submission queue associated with a Submission queue ID as documented in the Pending Write Command Queue 132 and detailed in Fig. 2. )
searching, based on the select memory address and the select submission queue identifier, a thread-tracking data structure for a select thread identifier associated with the select memory address; (Consistent with para [0025] of the instant application, a new thread is detected when a LBA is received from a host system request for a LBA that was not previously identified by an existing virtual thread. Thus a thread id is a means of tracking a series of non-sequential access requests. Examiner further notes that consistent with paragraphs [0017] and [0018] the source of the data may be a software application, database, or file systems. Thus the definition of a thread is broadly defined and is simply a source of data. Ramalingam [0030] discloses that the system may use a LBA to identify a sequential write stream and each sequential write stream has a unique sequential write stream identifier. Thus the write stream identifier of Ramalingam is an example of a thread id associated with the select memory address and the Pending Write Command Queue 132 is an example of a thread-tracking data structure associated for a select thread identifier (the write stream identifier) associated with the LBA (the select memory address).) the thread-tracking data structure comprising a set of entries (Ramalingam Fig. 2 and [0027]-[0029] that shows a set of entries 712a to 712n. )
and each entry in the set of entries storing: a single submission queue identifier; (Ramalingam Fig. 2 and [0027]-[0029] that discloses Queue Entry Field 714b that that stores a single submission queue id for each entry.) … and a single last memory address associated with a pair of the single submission queue identifier (Ramalingam Fig. 2 and [0027]0[0029 teaches a logical block address associated with the last memory address for the command associated with the command when it was placed in the queue, along with the submission queue ID.) …
the searching comprising determining … and that the select memory address precedes a given last memory address stored in the given entry; (Ramalingam [0059] discloses that upon initiation of sequential write stream detection, the value of the head entry 712c may be checked and compared to the command parameters stored in the prior history entry which is entry 712b. Thus the select memory address may be the address of 712b that precedes the last memory addressed stored in the head entry 712b which sequentially follows 712b per Ramalingam [0058].)
…
in response to finding the select thread identifier … causing the select write request to be processed based on the select thread identifier, (Ramalingam [0031] discloses that upon identifying a sequential write stream (identifier) the system will aggregate the write with previous writes requests using data aggregation logic 304. The Detection History Data Structure 724 that tracks how data is processed according to a write stream identifier is an example of a thread-tracking data structure used for processing the write request for the sequential write stream. Ramalingam [022] discloses the writes streams may be assigned a write steam identification (i.e. a thread identifier).)
However, Ramalingam does not explicitly disclose and each entry in the set of entries storing: … a single thread identifier; and
a single last memory address associated with a pair of the single submission queue identifier and the single thread identifier
the searching comprising determining that the select thread identifier is found in a given entry of the thread-tracking data structure and that a given thread identifier of the given entry is the select thread identifier in response to determining that the given entry is storing the select submission queue identified
causing the select write request to be processed based on the select thread identifier comprising storing the select thread identifier as metadata on the memory device in association with data written by the select write request; and updating the thread-tracking data structure based on the select write request, the select memory address, and the select thread identifier, and
during a garbage collection operation, migrating stored data associated with a common stored thread identifier together.
Navon, of a similar field of endeavor, further discloses and each entry in the set of entries storing: … a single thread identifier; (Navon [0036], [0127]-[0128] discloses a single source may be associated with a single physical host device and a namespace. Thus the namespace may be an example of a single thread identifier given it further refines the source of data for a given host. Navon [0131] discloses the namespace may be passed in the command along with a queue identifier. Namespaces allows the system to identify the memory with a finer granularity than using the submission queue id that may be associated with a single host as a plurality of namespaces may be referenced by a single host.
Ramalingam [0030] discloses a write stream identifier that is an example of a thread id is determined but does not necessarily store the write stream identifier. Navon discloses including with each command with a namespace, which helps identify a sequential sequence of command. Thus Ramalingam in view of Navon would store the namespace in the elements of Fig. 2 of Ramalingam as well as the submission queue id and the LBA to more accurately identify sequential data from a single source.)
and a single last memory address associated with a pair of the single submission queue identifier and the single thread identifier (Navon [0127]-[0128] discloses adding a namespace (a thread identifier) into the command queue and storing it in its command history. Thus will add the namespace (thread identifier) to the command history of Ramalingam shown in Fig. 2.)
the searching comprising determining that the select thread identifier is found in a given entry of the thread-tracking data structure and that a given thread identifier of the given entry is the select thread identifier in response to determining that the given entry is storing the select submission queue identified (Navon [0131] discloses that when searching a history for to identify sequential data, both the queue identifier (i.e. the submission queue identifier) and the namespace (i.e. the thread identifier) are used to determine if a potential read request is sequential to another read request. Thus if the thread identifier of an inbound request matches a thread identifier of an historical request, it will then make a determination if the namespace (i.e. the thread id) matches to make a determination if two commands may be sequential.)
causing the select write request to be processed based on the select thread identifier comprising storing the select thread identifier as metadata on the memory device in association with data written by the select write request; (Consistent with paras [0011], [0027], and [0066] metadata may be data relating to a host request such as a LBA or a thread id that describe the request. Navon [0064] discloses upon receipt of a new command the command history datastore 117 will be updated to include the most recent command data. Thus the data such as the submission queue identifier, a thread identifier, and/or the LBA of the history database that is metadata is stored on the memory device in association with a request (that may be a read or write request) in association with data written by a select write request).
and updating the thread-tracking data structure based on the select write request, the select memory address, and the select thread identifier, and (Navon [0064] discloses that the command history will be updated. (Navon [0131]-[0133] discloses both a namespace (thread Id) and a LBA may be used to determine if two commands are potentially sequential. Thus for a write request, the LBA (the select memory address) and the namespace (the select thread identifier) is updated in the command history (the tread tracking data structure).)
Ramalingam and Navon are in a similar field of endeavor as both relate to tracking incoming requests and making a determination if the requests are sequential. Thus it would have been obvious to a person of ordinary skill in the arts before the effectively filed date of the claimed invention to incorporate the namespace tracking of the source of data along with a submission queue identifier that identifies the host/submission queue id for a request, thus combining prior art elements according to known methods to yield predictable results (enable a single processor to send requests from multiple separate applications that may be using separate memory namespaces. Thus enabling efficient identification of sequential data that comes from a single application when a single host may be supporting multiple applications, each using their own namespace.)
The motivation to combine Navon into Ramalingam for claims 2-9 is the same as presented in claim 1 above.
However the combination of Ramalingam and Navon does not explicitly disclose and during a garbage collection operation, migrating stored data associated with a common stored thread identifier together.
Fischer, of a similar field of endeavor further discloses and during a garbage collection operation, migrating stored data associated with a common stored thread identifier together. (Fischer [0032] discloses multi-stream requests are classified to a stream ID. Fischer Figs. 10A and 10B and para [0102]-[0104] shows as writes arrive they are associated with a stream ID which is saved. See Fischer Fig. 10A step 1020. Fischer [0028] discloses that the stream ids are used when the system undergoes garbage collection to group together associated data for storing pages with a similar stream id in the same erased block. Thus Ramalingam in view of Navon and Fisher would maintain a stream id associated with the data written, and upon garbage collection would collect valid pages from separate garbage collected blocks into a single erased block when they are to the same stream id.)
Ramalingam, Navon, and Fischer are in a similar field of endeavor as all relate to managing flash memory in a multi-stream environment. Thus it would have been obvious to a person of ordinary skill in the art before the effectively filed date of the claimed invention to incorporate collecting pages from the same stream into a single block as taught by Fischer into the solution of Ramalingam and Navon that manages sequential access, thus combining prior art elements according to known methods to produce predictable results (extend the benefits of multi-stream SSDs for user writes to improve garbage collection efficiency. See Fischer [0043].)
The motivation to combine Fischer into the solution of Ramalingam and Navon for claims 2-9 is the same as presented in claim 1 above.
Regarding claim 2, The combination of Ramalingam, Navon, and Fischer teaches all of the limitations of claim 1 above. Ramalingam further teaches wherein the causing of the select write request to be performed based on the select thread identifier comprises: causing write data from the select write request to be written to a data storage area of the memory device associated with the select thread identifier. (Ramalingam Fig. 4 and supporting paras [0035]-[0042] discloses that once the write stream data structure is identified, the system proceeds to process the write request in the relevant Write Data Aggregation Storage Area 400a to 400d (the target of the SSD Nonvolatile Storage 120 per Fig. 1 of Ramalingam.).)
Regarding claim 3, The combination of Ramalingam, Navon, and Fischer teaches all of the limitations of claim 1 above. Ramalingam further teaches causing the select write request to be performed based on the new thread identifier; (Ramalingam Fig. 4 and supporting paras [0035]-[0042] discloses that once the write stream data structure is identified, the system proceeds to process the write request in the relevant Write Data Aggregation Storage Area 400a to 400d (the target of the SSD Nonvolatile Storage 120 per Fig. 1 of Ramalingam.) for the appropriate write stream id (per the thread id) and the write command may be the first write command associated with a write stream id (thus based on a new write string id (new thread identifier.).
Navon further teaches wherein the operations comprise: in response to not finding the select thread identifier in the thread-tracking data structure: determining a new thread identifier for the select write request; (Navon [0064] discloses upon receipt of a new command the command history datastore 117 will be updated to include the most recent command data. This will be done for all command histories, thus also in response to not finding the select thread identifier as matching an existing record, and will writing this to the command history will be determining a new thread id for the inbound (i.e. select) write request).)
… and updating the thread-tracking data structure based on the select write request, the select memory address, and the new thread identifier. (Navon [0064] discloses the system will update the command history based on an inbound (select) write request, thus will update the LBA (select memory address) and namespace (the new thread id) in the history database.)
The motivation to combine Navon into the existing combination is the same as described in claim 1 above.
Regarding claim 6, The combination of Ramalingam, Navon, and Fischer teaches all of the limitations of claim 1 above. Ramalingam further teaches wherein the searching of the thread-tracking data structure for the select thread identifier based on the select memory address and the select queue identifier comprises: determining that no entry in the thread-tracking data structure associated with the select queue identifier is storing a first last memory address that precedes the select memory address; and in response to determining that no entry in the thread-tracking data structure associated with the select queue identifier is storing the first last memory address that precedes the select memory address: for an individual entry of the thread-tracking data structure associated with another queue identifier, determining whether a second last memory address stored in the individual entry precedes the select memory address; and in response to determining that the second last memory address precedes the select memory address, determining that an individual thread identifier associated with the individual entry is the select thread identifier. (Ramalingam [0063] discloses at block 74- of Fig. 6 the system compares the LBA address of an inbound write request to the last LBA of the next entry (112 d shown in Fig. 2 of Ramalingam) to determine if the two writes are sequential and assumes the inbound write request is associated with a sequential write stream when the addresses indicate the two entries are likely write commands of an individual sequential write stream and are associated with a write stream id (the thread identifier).)
Regarding claim 8, The combination of Ramalingam, Navon, and Fischer teaches all of the limitations of claim 1 above. Ramalingam further teaches wherein the causing of the select write request to be performed based on the select thread identifier comprises: adding the select write request to a list of write requests that is associated with the select thread identifier. (Ramalingam [0027] discloses that data is received to a common pending write command queue 132, the write stream management 136 associates the commands with a specific write stream, and transfers the command associated with a write stream to a Transfer Buffer Storage 140 queue associated with the write stream (i.e. to a specific associated Buffer partition for the write stream).)
Regarding claim 9, The combination of Ramalingam, Navon, and Fischer teaches all of the limitations of claim 8 above. Ramalingam further teaches wherein the operations comprise: determining whether a set of conditions is satisfied for executing write requests from the list of write requests associated with the select thread identifier; and in response to determining that the set of conditions is satisfied for executing write requests from the list of write requests associated with the select thread identifier, causing at least some portion of write requests from the list of write requests associated with the select thread identifier to be executed. (Ramalingam [0032] discloses that the write requests from the Transfer Buffer Storage 140 may be aggregated into sequential write request and written to the appropriate nonvolatile storage regions 160 a to n.)
Regarding claim 10, Ramalingam teaches At least one non-transitory machine-readable storage medium comprising instructions that, when executed by a processing device of a memory sub-system, cause the processing device to perform operations comprising: (Ramalingam [0141] teaches the operations may be implemented as a method, apparatus, or computer program code maintained in a computer readable storage medium, that causes the processor to perform the operations of Block Storage Controller 110.)
receiving a set of command requests from a host system, (Ramalingam [0026] discloses computing system 100 that may be a person computer, a mainframe, a telephony deice, a smart phone, etc. that sends read, write or other storage commands. Ramalingam [0027] discloses the commands received from the host are placed in a Pending Write Command Queue 132 where the format of the Pending Write Command Queue 132 is detailed in Fig. 2 and paras [0027]-[0028].) the memory sub-system comprising a plurality of submission queues, (Ramalingam [0002] discloses the host presents requests to one or more storage command submission queues.) each submission queue of the plurality of submission queues associated with a corresponding submission queue identifier, (Ramalingam Fig. 2 and supporting para [0057] discloses each pending write command may contain a submission Queue ID that identifies the source of the particular submission queue of each pending write command, thus each submission queue has an associated qid.) each submission queue identifier being associated with at least one hardware processor core of the host system, (Ramalingam [0055] discloses the write commands were received from multiple submission queues 124 a, 124, . . . 124 n from multiple processor nodes 104 a, 104 b . . . 104 n, thus each submission queue is associated with a queue identifier and is associated with a processor node.)
each individual command request in the set of command requests comprising an individual submission queue identifier and being stored to an individual submission queue of the plurality of submission queues associated with the individual submission queue identifier; (Ramalingam Fig. 2 and paras [0027], and [0056]-[0058] discloses commands received from the host and placed in the Pending Write Command Queue 132 contains a Submission Queue ID that identifies one of the multiple submission queues 124 a, 124, . .. 124 n, thus each entry in queue 132 is a command request comprising an individual queue identifier and was stored to an individual submission queue of the multiple submission queues.)
obtaining, from a select submission queue of the plurality of submission queues, a select write request that comprises a select memory address, the select submission queue being associated with a select submission queue identifier; (Ramalingam [0027] discloses the block storage controller 110 receives write commands from the various submission queues 124a to 124n that contain a LBA, the submission queue associated with a Submission queue ID as documented in the Pending Write Command Queue 132 and detailed in Fig. 2. )
searching, based on the select memory address and the select submission queue identifier, a thread-tracking data structure for a select thread identifier associated with the select memory address; (Consistent with para [0025] of the instant application, a new thread is detected when a LBA is received from a host system request for a LBA that was not previously identified by an existing virtual thread. Thus a thread id is a means of tracking a series of non-sequential access requests. Examiner further notes that consistent with paragraphs [0017] and [0018] the source of the data may be a software application, database, or file systems. Thus the definition of a thread is broadly defined and is simply a source of data. Ramalingam [0030] discloses that the system may use a LBA to identify a sequential write stream and each sequential write stream has a unique sequential write stream identifier. Thus the write stream identifier of Ramalingam is an example of a thread id associated with the select memory address and the Pending Write Command Queue 132 is an example of a thread-tracking data structure associated for a select thread identifier (the write stream identifier) associated with the LBA (the select memory address).) the thread-tracking data structure comprising a set of entries (Ramalingam Fig. 2 and [0027]-[0029] that shows a set of entries 712a to 712n. )
and each entry in the set of entries storing: a single submission queue identifier; (Ramalingam Fig. 2 and [0027]-[0029] that discloses Queue Entry Field 714b that that stores a single submission queue id for each entry.) … and a single last memory address associated with a pair of the single submission queue identifier (Ramalingam Fig. 2 and [0027]0[0029 teaches a logical block address associated with the last memory address for the command associated with the command when it was placed in the queue, along with the submission queue ID.) …
the searching comprising determining … and that the select memory address precedes a given last memory address stored in the given entry; (Ramalingam [0059] discloses that upon initiation of sequential write stream detection, the value of the head entry 712c may be checked and compared to the command parameters stored in the prior history entry which is entry 712b. Thus the select memory address may be the address of 712b that precedes the last memory addressed stored in the head entry 712b which sequentially follows 712b per Ramalingam [0058].)
in response to not finding the select thread identifier in the thread-tracking data structure: determining a new thread identifier for the select write request; (Ramalingam [0031] discloses that upon identifying a sequential write stream (identifier) the system will aggregate the write with previous writes requests using data aggregation logic 304. Thus the Detection History Data Structure 724 that tracks how data is processed according to a write stream identifier is an example of a thread-tracking data structure.)
causing the select write request to be performed based on the new thread identifier; (Ramalingam [0031] discloses that upon identifying a sequential write stream (identifier) the system will aggregate the write with previous writes requests using data aggregation logic 304. Thus the Detection History Data Structure 724 that tracks how data is processed according to a write stream identifier is an example of a thread-tracking data structure.)
However, Ramalingam does not explicitly disclose and each entry in the set of entries storing: … a single thread identifier; and
a single last memory address associated with a pair of the single submission queue identifier and the single thread identifier
the searching comprising determining that the select thread identifier is found in a given entry of the thread-tracking data structure and that a given thread identifier of the given entry is the select thread identifier in response to determining that the given entry is storing the select submission queue identified
the causing the select write request to be processed based on the new thread identifier comprising storing the new thread identifier as metadata on the memory device in association with data written by the select write request; and updating the thread-tracking data structure based on the select write request, the select memory address, and the select thread identifier, and
during a garbage collection operation, migrating stored data associated with a common stored thread identifier together.
Navon, of a similar field of endeavor, further discloses and each entry in the set of entries storing: … a single thread identifier; (Navon [0127]-[0128] discloses a single namespace may be associated with a single host processor where a single host processor may be an example of a single thread identifier (given it is a source of data) and thus the namespace is an example of a thread identifier. Navon [0131] discloses the namespace which may be passed in the command along with a queue identifier. ) and a single last memory address associated with a pair of the single submission queue identifier and the single thread identifier (Navon [0127]-[0128] discloses adding a namespace (a thread identifier) into the command queue and storing it in its command history. Thus will add the namespace (thread identifier) to the command history of Ramalingam shown in Fig. 2.)
the searching comprising determining that the select thread identifier is found in a given entry of the thread-tracking data structure and that a given thread identifier of the given entry is the select thread identifier in response to determining that the given entry is storing the select submission queue identified (Navon [0131] discloses that when searching a history for to identify sequential data, both the queue identifier (i.e. the submission queue identifier) and the namespace (i.e. the thread identifier) are used to determine if a potential read request is sequential to another read request. Thus if the thread identifier of an inbound request matches a thread identifier of an historical request, it will then make a determination if the namespace (i.e. the thread id) matches to make a determination if two commands may be sequential.)
the causing of the select write request to be performed based on the new thread identifier comprising storing the new thread identifier as metadata on the memory device in association with data written by the select write request; (Consistent with paras [0011], [0027], and [0066] metadata may be data relating to a host request such as a LBA or a thread id that describe the request. Navon [0064] discloses upon receipt of a new command the command history datastore 117 will be updated to include the most recent command data. Thus the data such as the submission queue identifier, a thread identifier, and/or the LBA of the history database that is metadata is stored on the memory device in association with a request (that may be a read or write request) in association with data written by a select write request).
and updating the thread-tracking data structure based on the select write request, the select memory address, and the select thread identifier, and (Navon [0064] discloses that the command history will be updated. (Navon [0131]-[0133] discloses both a namespace (thread Id) and a LBA may be used to determine if two commands are potentially sequential. Thus for a write request, the LBA (the select memory address) and the namespace (the select thread identifier) is updated in the command history (the tread tracking data structure).)
Ramalingam and Navon are in a similar field of endeavor as both relate to tracking incoming requests and making a determination if the requests are sequential. Thus it would have been obvious to a person of ordinary skill in the arts before the effectively filed date of the claimed invention to incorporate the namespace tracking of the source of data along with a submission queue identifier that identifies the host/submission queue id for a request, thus combining prior art elements according to known methods to yield predictable results (enable a single processor to send requests from multiple separate applications that may be using separate memory namespaces. Thus enabling efficient identification of sequential data when a single host may be supporting multiple applications (each using their own namespace).)
The motivation to combine Navon into Ramalingam for claims 2-9 is the same as presented in claim 1 above.
However the combination of Ramalingam and Navon does not explicitly disclose and during a garbage collection operation, migrating stored data associated with a common stored thread identifier together.
Fischer, of a similar field of endeavor further discloses and during a garbage collection operation, migrating stored data associated with a common stored thread identifier together. (Fischer [0032] discloses multi-stream requests are classified to a stream ID. Fischer Figs. 10A and 10B and para [0102]-[0104] shows as writes arrive they are associated with a stream ID which is saved. See Fischer Fig. 10A step 1020. Fischer [0028] discloses that the stream ids are used when the system undergoes garbage collection to group together associated data for storing pages with a similar stream id in the same erased block. Thus Ramalingam in view of Navon and Fisher would maintain a stream id associated with the data written, and upon garbage collection would collect valid pages from separate garbage collected blocks into a single erased block when they are to the same stream id.)
Ramalingam, Navon, and Fischer are in a similar field of endeavor as all relate to managing flash memory in a multi-stream environment. Thus it would have been obvious to a person of ordinary skill in the art before the effectively filed date of the claimed invention to incorporate collecting pages from the same stream into a single block as taught by Fischer into the solution of Ramalingam and Navon that manages sequential access, thus combining prior art elements according to known methods to produce predictable results (extend the benefits of multi-stream SSDs for user writes to improve garbage collection efficiency. See Fischer [0043].)
The motivation to combine Fischer into the solution of Ramalingam and Navon for claims 2-9 is the same as presented in claim 1 above.
Regarding claim 11, The combination of Ramalingam, Navon, and Fischer teaches all of the limitations of claim 10 above.
The remainder of claim 11 recites limitations found in claim 2 above and thus is rejected based on the teachings and rationale of claim 2 above.
Regarding claim 12, The combination of Ramalingam, Linkovsky and Fischer teaches all of the limitations of claim 10 above. Ramalingam further teaches wherein the operations comprise: in response to finding the select thread identifier in the thread-tracking data structure: causing the select write request to be processed based on the select thread identifier; (Ramalingam Fig. 4 and supporting paras [0035]-[0042] discloses that once the write stream data structure is identified, the system proceeds to process the write request in the relevant Write Data Aggregation Storage Area 400a to 400d (the target of the SSD Nonvolatile Storage 120 per Fig. 1 of Ramalingam.).)
Navon further teaches and updating the thread-tracking data structure based on the select write request, the select memory address, and the select thread identifier. (Navon [0064] discloses that the command history will be updated. Navon [0131]-[0133] discloses both a namespace (thread Id) and a LBA may be used to determine if two commands are potentially sequential. Thus for a write request, the LBA (the select memory address) and the namespace (the select thread identifier) is updated in the command history (the tread tracking data structure).)
The motivation to combine Navon into the existing combination is the same as set forth in claim 10 above.
Regarding claim 15, The combination of Ramalingam, Linkovsky and Fischer teaches all of the limitations of claim 10 above.
The remainder of claim 15 recites limitations found in claim 6 above and thus is rejected based on the teachings and rationale of claim 6 above.
Regarding claim 16, The combination of Ramalingam, Linkovsky and Fischer teaches all of the limitations of claim 10 above.
The remainder of claim 16 recites limitations found in claim 7 above and thus is rejected based on the teachings and rationale of claim 7 above.
Regarding claim 17, The combination of Ramalingam, Linkovsky and Fischer teaches all of the limitations of claim 10 above.
The remainder of claim 17 recites limitations found in claim 8 above and thus is rejected based on the teachings and rationale of claim 8 above.
Regarding claim 18, The combination of Ramalingam, Linkovsky and Fischer teaches all of the limitations of claim 17 above.
The remainder of claim 18 recites limitations found in claim 9 above and thus is rejected based on the teachings and rationale of claim 9 above.
Regarding claim 19, Ramalingam teaches A method comprising: (Ramalingam [0141] teaches the operations may be implemented as a method, apparatus, or computer program code maintained in a computer readable storage medium, that causes the processor to perform the operations of Block Storage Controller 110.)
receiving, at a memory sub-system, a set of command requests from a host system, (Ramalingam [0026] discloses computing system 100 (a memory sub-system) that may be a person computer, a mainframe, a telephony deice, a smart phone, etc. that sends read, write or other storage commands from Processor Nodes (where each processor node is an example of a host). Ramalingam [0027] discloses the commands received from the host are placed in a Pending Write Command Queue 132 where the format of the Pending Write Command Queue 132 is detailed in Fig. 2 and paras [0027]-[0028].) -
the memory sub-system comprising a plurality of submission queues, (Ramalingam [0002] discloses the host presents requests to one or more storage command submission queues.) each submission queue of the plurality of submission queues being associated with a corresponding submission queue identifier, (Ramalingam Fig. 2 and supporting para [0057] discloses each pending write command may contain a submission Queue ID that identifies the source of the particular submission queue of each pending write command, thus each submission queue has an associated qid.) each submission queue identifier being associated with at least one hardware processor core of the host system, each individual command request in the set of command requests comprising an individual submission queue identifier and being stored to an individual submission queue of the plurality of submission queues associated with the individual submission queue identifier; (Ramalingam [0055] discloses the write commands were received from multiple submission queues 124 a, 124, . . . 124 n from multiple processor nodes 104 a, 104 b . . . 104 n, thus each submission queue is associated with a queue identifier and is associated with a processor node.)
and scanning, by a processing device of the memory sub-system, one or more submission queues of the plurality of submission queues for command requests to be executed, the scanning being configured to: (Ramalingam [0002]-[0003] discloses the controller accesses the submission queues using an access distribution process such as a “round robin” distribution to obtain a command, including write commands, and places the command in the common pending queue)
The remainder of claim 19 recites limitations described in claim 1 above and thus is rejected based on the teaching and rationale of claim 1 above.
Regarding claim 20, The combination of Ramalingam, Navon, and Fischer teaches all of the limitations of claim 19 above.
The remainder of claim 20 recites limitations found in claim 3 above and thus is rejected based on the teachings and rationale of claim 3 above.
Regarding claim 22, The combination of Ramalingam, Navon, and Fischer teaches all of the limitations of claim 19 above.
The remainder of claim 22 recites limitations found in claim 8 above and thus is rejected based on the teachings and rationale of claim 8 above.
Regarding claim 23, The combination of Ramalingam, Navon, and Fischer teaches all of the limitations of claim 22 above. Ramalingam further teaches determining that a set of conditions is satisfied for executing write requests from the list of write requests associated with the select thread identifier; and in response to determining that the set of conditions is satisfied for executing write requests from the list of write requests associated with the select thread identifier, causing at least some portion of write requests from the list of write requests associated with the select thread identifier to be executed. (Ramalingam [0032] discloses that the write requests from the Transfer Buffer Storage 140 may be aggregated into sequential write request and written to the appropriate nonvolatile storage regions 160 a to n.)
Claims 7 and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Ramalingam (RAMALINGAM US 2016/0283116 A1 published 9/29/2016 by Intel Corporation) and in view of Navon (Navon et al., us 2020/0242037 A1) and Fischer (FISCHER et al., US 2018/0307598 A1) as detailed in claims 1 and X above and further in view of Linkovsky (Linkovsky et al., US 10,564,853 B2 published 2/18/2020 by Western Digital Technologies, Inc.).
Regarding claim 7, The combination of Ramalingam, Navon, and Fischer teaches all of the limitations of claim 1 above. However the combination does not explicitly teach wherein the operations comprise: determining whether the select thread identifier satisfies a set of pruning criteria; and in response to determining that the select thread identifier satisfies the set of pruning criteria, updating the thread-tracking data structure to remove one or more entries associated with the select thread identifier from the thread-tracking data structure.
Linkovsky further teaches wherein the operations comprise: determining whether the select thread identifier satisfies a set of pruning criteria; and in response to determining that the select thread identifier satisfies the set of pruning criteria, updating the thread-tracking data structure to remove one or more entries associated with the select thread identifier from the thread-tracking data structure. (Linkovsky column 19 lines 6-12 teaches that the entries of the Stream Detection Manager (SDM) may be checked to determine if they used be removed based on the “oldness” using a least recently used (LRU) methodologies and will removed entries that meet a ”oldness” test (i.e. the pruning criteria).)
Ramalingam, Navon, Fischer, and Linkovsky are in a similar field of endeavor as all relate to tracking incoming requests, identifying sequential streams of data, and making decisions on subsequent requests based on the characteristics of the subsequent requests and prior streams to facilitate sequentially handling requests that leads to more efficient handling of the requests. Thus it would have been obvious to a person of ordinary skill in the arts before the effectively filed date of the claimed invention to incorporate the SDM data structure pruning method for managing the sequential tracking data structures as taught by Linkovsky into the solution of Ramalingam, Navon, and Fisher that tracks sequential data processing using tracking data structures (combining prior art elements according to known methods) to enable create room for newly identified sequential streams when the sequential stream tracking data structures are limited in size and only a finite number of write streams may be tracked (to yield predictable results).
Regarding claim 21, The combination of Ramalingam, Navon, and Fischer teaches all of the limitations of claim 19 above.
The remainder of claim 21 recites limitations found in claim 7 above and thus is rejected based on the teachings and rationale of claim 7 above.
Response to Remarks
Examiner thanks Applicant for their claim amendments and remarks of 2/18/2026. They have been fully considered.
Examiner agrees the claims as amended are not taught within the prior citations. Therefore the rejection has been withdrawn.
However, upon further consideration, a new ground(s) of rejection is made in view of newly cited Navon (Navon et al., us 2020/0242037 A1)
With respect to independent claims 1, 10, and 19, Ramalingam in view of Navon and Fisher teaches the amended limitations as detailed above.
Navon [0036], [0127]-[0128] discloses a single source may be associated with a single physical host device and a namespace. Thus the namespace may be an example of a single thread identifier given it further refines the source of data for a given host. Navon [0131] discloses the namespace may be passed in the command along with a queue identifier. Namespaces allows the system to identify the memory with a finer granularity than using the submission queue id that may be associated with a single host as a plurality of namespaces may be referenced by a single host.
Ramalingam [0030] discloses a write stream identifier that is an example of a thread id is determined but does not necessarily store the write stream identifier. Navon discloses including with each command with a namespace, which helps identify a sequential sequence of command. Thus Ramalingam in view of Navon would store the namespace in the elements of Fig. 2 of Ramalingam as well as the submission queue id and the LBA to more accurately identify sequential data from a single source for the instance when a plurality of applications from a single host send data from a single submission queue, and the applications use separate namespaces.
Applicants arguments with respect to dependent claims 2-9, 11-18, and 20 all reply upon perceived errors in the base claims and thus has been addressed in the rejection and remarks related to independent claims 1, 10, and 19.
Conclusion
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/JANICE M. GIROUARD/Primary Examiner, Art Unit 2138