DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No.11,742,040. Although the claims at issue are not identical, they are not patentably distinct from each other because they contain substantially similar subject matter (see chart below).
Claims 2-5, 7-11, 13-15 and 17-20 are also rejected as being dependent on claims 1, 6, 12, 16 and may also correspond to claims 2-5, 7-11, 13-15 and 17-20 of the ‘040 patent.
Instant Application
US Patent No. 11,742,040
1. A memory system comprising: a nonvolatile memory (NVM) including a first NVM chip and a second NVM chip; and a controller configured to control the NVM, wherein the controller comprises: a data pin configured to receive read data through a data bus during a read operation; a data strobe pin configured to receive a data strobe signal through a data strobe signal bus during the read operation; a read enable pin configured to transmit a read enable signal through a read enable signal bus during the read operation, the read enable signal comprising a preamble section, a toggling section and a postamble section; and an on-die termination (ODT) pin configured to transmit an ODT signal during the read operation, wherein the ODT signal enables and disables termination on at least one of the data bus, the data strobe signal bus, or the read enable signal bus, wherein the termination is enabled during the preamble section of the read enable signal after the read enable signal falling, and the termination is disabled during the postamble section of the read enable signal, wherein the first NVM chip includes a first ODT circuit, and the first ODT circuit is used to perform an ODT when the read data is read from the second NVM chip and the ODT signal is enabled.
1. A memory system comprising: a nonvolatile memory (NVM) including a first NVM chip and a second NVM chip; and a controller configured to control the NVM, wherein the controller comprises: a data pin configured to receive read data through a data bus during a read operation; a data strobe pin configured to receive a data strobe signal through a data strobe signal bus during the read operation; a read enable pin configured to transmit a read enable signal through a read enable signal bus during the read operation, the read enable signal comprising a preamble section, a toggling section and a postamble section; and an on-die termination (ODT) pin configured to transmit an ODT signal during the read operation, wherein the ODT signal enables and disables termination on at least one of the data bus, the data strobe signal bus, and the read enable signal bus of the NVM, wherein the termination is enabled during the preamble section of the read enable signal after the read enable signal falling, and the termination is disabled during the postamble section of the read enable signal, wherein the first NVM chip includes a first ODT circuit, and the first ODT circuit is used to perform the ODT when the read data is read from the second NVM chip.
6. A memory system comprising: a nonvolatile memory (NVM) including a first NVM chip and a second NVM chip; and a controller configured to control the NVM, wherein the controller comprises: a data pin configured to transmit write data through a data bus during a write operation; a data strobe pin configured to transmit a data strobe signal through a data strobe signal bus during the write operation, the data strobe signal comprising a preamble section, a toggling section and a postamble section; and an on-die termination (ODT) pin configured to transmit an ODT signal during the write operation, wherein the ODT signal enables and disables termination on at least one of the data bus, the data strobe signal bus, or a read enable signal bus, wherein the termination is enabled during the preamble section of the data strobe signal after the data strobe signal falling, and the termination is disabled during the postamble section of the data strobe signal, wherein the first NVM chip includes a first ODT circuit, and the first ODT circuit is used to perform an ODT when the write data is written to the second NVM chip and the ODT signal is enabled.
6. A memory system comprising: a nonvolatile memory (NVM) including a first NVM chip and a second NVM chip; and a controller configured to control the NVM, wherein the controller comprises: a data pin configured to transmit write data through a data bus during a write operation; a data strobe pin configured to transmit a data strobe signal through a data strobe signal bus during the write operation, the data strobe signal comprising a preamble section, a toggling section and a postamble section; and an on-die termination (ODT) pin configured to transmit an ODT signal during the write operation, wherein the ODT signal enables and disables termination on at least one of the data bus, the data strobe signal bus, and a read enable signal bus of the NVM, wherein the termination is enabled during the preamble section of the data strobe signal after the data strobe signal falling, and the termination is disabled during the postamble section of the data strobe signal, wherein the first NVM chip includes a first ODT circuit, and the first ODT circuit is used to perform the ODT when the write data is written to the second NVM chip.
12. A nonvolatile memory (NVM) device comprising: a first NVM chip and a second NVM chip; a data pin configured to transmit read data to a controller through a data bus during a read operation; a data strobe pin configured to transmit a data strobe signal to the controller through a data strobe signal bus during the read operation; a read enable pin configured to receive a read enable signal from the controller through a read enable signal bus during the read operation, the read enable signal comprising a preamble section, a toggling section and a postamble section; and an on-die termination (ODT) pin configured to receive an ODT signal from the controller during the read operation, wherein the ODT signal enables and disables termination on at least one of the data bus, the data strobe signal bus, or the read enable signal bus, wherein the termination is enabled during the preamble section of the read enable signal after the read enable signal falling, and the termination is disabled during the postamble section of the read enable signal, wherein the first NVM chip includes a first ODT circuit, and the first ODT circuit is used to perform an ODT when the read data is read from the second NVM chip and the ODT signal is enabled.
12. A nonvolatile memory (NVM) device comprising: a first NVM chip and a second NVM chip; a data pin configured to transmit read data to a controller through a data bus during a read operation; a data strobe pin configured to transmit a data strobe signal to the controller through a data strobe signal bus during the read operation; a read enable pin configured to receive a read enable signal from the controller through a read enable signal bus during the read operation, the read enable signal comprising a preamble section, a toggling section and a postamble section; and an on-die termination (ODT) pin configured to receive an ODT signal from the controller during the read operation, wherein the ODT signal enables and disables termination on at least one of the data bus, the data strobe signal bus, and the read enable signal bus, wherein the termination is enabled during the preamble section of the read enable signal after the read enable signal falling, and the termination is disabled during the postamble section of the read enable signal, wherein the first NVM chip includes a first ODT circuit, and the first ODT circuit is used to perform the ODT when the read data is read from the second NVM chip.
16. A nonvolatile memory (NVM) device comprising: a first NVM chip and a second NVM chip; a data pin configured to receive write data from a controller through a data bus during a write operation; a data strobe pin configured to receive a data strobe signal from the controller through a data strobe signal bus during the write operation, the data strobe signal comprising a preamble section, a toggling section and a postamble section; and an on-die termination (ODT) pin configured to receive an ODT signal from the controller during the write operation, wherein the ODT signal enables and disables termination on at least one of the data bus, the data strobe signal bus, or a read enable signal bus, wherein the termination is enabled during the preamble section of the data strobe signal after the data strobe signal falling, and the termination is disabled during the postamble section of the data strobe signal, wherein the first NVM chip includes a first ODT circuit, and the first ODT circuit is used to perform an ODT when the write data is written to the second NVM chip and the ODT signal is enabled.
16. A nonvolatile memory (NVM) device comprising: a first NVM chip and a second NVM chip; a data pin configured to receive write data from a controller through a data bus during a write operation; a data strobe pin configured to receive a data strobe signal from the controller through a data strobe signal bus during the write operation, the data strobe signal comprising a preamble section, a toggling section and a postamble section; and an on-die termination (ODT) pin configured to receive an ODT signal from the controller during the write operation, wherein the ODT signal enables and disables termination on at least one of the data bus, the data strobe signal bus, and a read enable signal bus of the NVM device, wherein the termination is enabled during the preamble section of the data strobe signal after the data strobe signal falling, and the termination is disabled during the postamble section of the data strobe signal, wherein the first NVM chip includes a first ODT circuit, and the first ODT circuit is used to perform the ODT when the write data is written to the second NVM chip.
Response to Arguments
Applicant’s arguments/amendments filed 2/6/2026, with respect to the rejection of claims 1-20 under 35 U.S.C. 101 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new grounds of rejection is made under Nonstatutory Double Patenting as seen above.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/JASON M CRAWFORD/Primary Examiner, Art Unit 2844