Prosecution Insights
Last updated: October 25, 2026
Application No. 18/776,624

FLIP-CHIP LIGHT EMITTING DIODE AND MANUFACTURING METHOD THEREOF

Non-Final OA §102§103§112
Filed
Jul 18, 2024
Priority
Jan 31, 2024 — TW 113103849
Examiner
REIDA, MOLLY KAY
Art Unit
2899
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Taiwan-Asia Semiconductor Corporation
OA Round
1 (Non-Final)
82%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
86%
With Interview

Examiner Intelligence

Grants 82% — above average
82%
Career Allowance Rate
367 granted / 445 resolved
+14.5% vs TC avg
Minimal +3% lift
Without
With
+3.2%
Interview Lift
resolved cases with interview
Typical timeline
2y 2m
Avg Prosecution
16 currently pending
Career history
476
Total Applications
across all art units

Statute-Specific Performance

§101
0.2%
-39.8% vs TC avg
§103
50.2%
+10.2% vs TC avg
§102
30.0%
-10.0% vs TC avg
§112
17.6%
-22.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 445 resolved cases

Office Action

§102 §103 §112
DETAILED ACTION Priority Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. Information Disclosure Statement The information disclosure statement (IDS) submitted on 07/18/2024, 02/05/2025, 07/21/2025, and 07/23/2025 have been considered by the examiner. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claim 1-10 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Re claim 1, claim 1 recites “…removing the first substrate and forming a first electrode and a second electrode on a side of the semiconductor structure adjacent to the first substrate…”. This is unclear because the claim refers to “adjacent to the first substrate” after the substrate has been removed. Appropriate correction is required. Re claim 10, claim 10 is a device claim that is defined by a method (i.e. “product-by-process” (MPEP 2113)); however, determination of patentability is based on the product itself. It is unclear what aspects of the device defined by the process are intended to be covered by claim 10. The Examiner suggests cancellation of claim 10 or re-writing claim 10 as a pure device claim so that is clear what limitations are desired to be covered. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1-4, and 6-10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Varghese et al. (US Pub. 2020/0168766). Regarding independent claim 1, Varghese teaches a method for manufacturing a flip-chip light emitting diode (Figs. 1A-1E; para. 0048+), including the following steps: providing a first substrate (150) (Fig. 1A; para. 0048); performing an epitaxial process to form a semiconductor structure (10) on the first substrate, wherein the semiconductor structure includes a first semiconductor epitaxial layer (101), a light emitting layer (103), a second semiconductor epitaxial layer(102) and a current conduction layer (upper portion of 102) in sequence from adjacent to the first substrate, a bonding surface (10A) is formed by the current conductive layer and defines a first electrode projection area (portion to be opposite 121; refer to Fig. 1E) and a second electrode projection area (portion to be opposite 122; refer to Fig. 1E); performing a diffusion process toward the bonding surface by a diffusion material to form at least one path area (170) with a high doping concentration in the current conductive layer (Fig. 1B; para. 0049); performing a bonding process to bond a second substrate (140) to the bonding surface (Fig. 1C; para. 0050); and removing the first substrate and forming a first electrode (122) and a second electrode (122) on a side of the semiconductor structure adjacent to the first substrate, wherein a position of the first electrode corresponds to the first electrode projection area, and a position of the second electrode corresponds to the second electrode projection area (Figs. 1D-1E; para. 0051-0052). Re claim 2, Varghese teaches wherein the at least one path area is disposed the other position located outside a shortest connection path between the first electrode projection area and the second electrode projection area (Fig. 1E - at least the far right-hand side of 170 is outside of the shortest path). Re claim 3, Varghese teaches wherein the at least one path area is further disposed on a shortest connection path between the first electrode projection area and the second electrode projection area (Fig. 1E - at least the far left-hand side of 170 is on the shortest path). Re claim 4, Varghese teaches wherein each of the at least one path area is in the form of a long strip area (Fig. 1E). Re claim 6, Varghese teaches wherein before performing the bonding process, at least one bonding material (132) is coated to the bonding surface (Fig. 1C; para. 0050). Re claim 7, Varghese teaches wherein the diffusion material is selected from one of the following material groups consisting of magnesium and zinc (para. 0049). Re claim 8, Varghese teaches wherein the diffusion material is selected from the same type of material as the doping material of the current conduction layer (para. 0048, 0049 teaching both are p-type doped). Re claim 9, Varghese teaches wherein the current conduction path formed by each of the at least one path area has a resistance within a set range (this would necessarily exist as “within a set range” is non-limiting and the current conduction path formed by each of the at least one path area would inherently have a resistance). Re claim 10, Varghese teaches a flip-chip light emitting diode manufactured by the method for manufacturing the flip-chip light-emitting diode of claim 1 (Refer to rejection of claim 1). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 5 is rejected under 35 U.S.C. 103 as being unpatentable over Varghese et al. (US Pub. 2020/0168766). Re claim 5, Varghese is silent with respect to the “doping concentration of each of the at least one path area is 10 to 103 times the doping concentration of other areas in the current conduction layer other than the at least one path area”; however, Varghese does teach the doping concentration of the one path area is higher than the doping concentration of other areas in the current conduction layer for the purpose of forming an ohmic contact (para. 0038, 0041) and it would have been obvious to one of ordinary skill in the art at the time of filing to optimize the dopant concentration of each of the at least one path area to arrive at the claimed invention for the purpose of ensuring sufficient ohmic connection (MPEP 2144.05, II). Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: Herrmann (US Pub. 2022/0271196). Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOLLY KAY REIDA whose telephone number is (571)272-4237. The examiner can normally be reached M-F 8:30-5:00PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Brent Fairbanks can be reached at (408)918-7532. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MOLLY K REIDA/Examiner, Art Unit 2899
Read full office action

Prosecution Timeline

Jul 18, 2024
Application Filed
Oct 13, 2026
Non-Final Rejection mailed — §102, §103, §112 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
82%
Grant Probability
86%
With Interview (+3.2%)
2y 2m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 445 resolved cases by this examiner. Grant probability derived from career allowance rate.

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