DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-6, 8-11, and 13-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Iversen et al. (US 2013/0278317) in view of Englekirk et al. (US 2018/0337146).
Regarding claim 1, Iversen et al. discloses, as shown in Figures 2-4, a method of fabricating an integrated circuit including:
fabricating a plurality of series-coupled MOSFETs (32,76) on a silicon-on-insulator substrate [0030];
fabricating a plurality of contact (B), each contact having a first end in on a region of the substrate, and having a second end accessible to connections in a superstructure (64) of the integrated circuit;
fabricating a resistor (Rb) between the second ends of a pair of groups of the plurality of contacts, each resistor configured to provide substantial radio frequency isolation between the pair of groups.
Iversen et al. does not disclose the plurality of contacts being the substrate contacts, each substrate contact having a first end in close enough proximity to the substrate to impose a back bias voltage on a region of the substrate sufficient to increase the power handing capability of at least one of the MOSFETs. However, Englekirk et al. discloses a method of fabricating an integrated circuit including forming a plurality of contacts (1302a,1302b) being the substrate contacts, each substrate contact having a first end in close enough proximity to the substrate (402). Note Figures of Englekirk et al. Therefore, it would have been obvious to one of ordinary skills in the art at the time the invention was made to form the plurality of contact of Iversen et al. being the substrate contacts in close proximity to the substrate, such as taught by Englekirk et al. in order to further improve the power handling capability of the MOSFETs.
Regarding claims 2-3, 9-10, and 16-17, Eversen et al. and Englekirk et al. disclose the back bias voltage is a negative bias voltage, or a positive bias voltage (Table 1, Figures and their description). Iversen et al. and Englekirk et al. do not disclose the MOSFETs are N-type MOSFETs nor the MOSFETs are P-type MOSFETs. However, it would have been obvious to one of ordinary skills in the art at the time the invention was made to form the MOSFETs of Eversen et al. and Englekirk et al. being N-type MOSFETs or P-type MOSFETs depending on the desired circuit configuration.
Regarding claims 4, 11, and 18, Eversen et al. and Englekirk et al. do not disclose each resistor between the pair of groups having the claimed resistant value as claimed. However, the selection of these parameters such as energy, concentration, temperature, time, speed, molar fraction, depth, thickness, resistance, etc., would have been obvious and involve routine optimization which has been held to be within the level of ordinary skill in the art. "Normally, it is to be expected that a change in energy, concentration, temperature, time, molar fraction, depth, thickness, etc., or in combination of the parameters would be an unpatentable modification. Under some circumstances, however, changes such as these may impart patentability to a process if the particular ranges claimed produce a new and unexpected result which is different in kind and not merely degree from the results of the prior art... such ranges are termed "critical ranges and the applicant has the burden of proving such criticality.... More particularly, where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Alter 105 USPQ233, 255 (CCPA 1955). See also In re Waite 77 USPQ 586 (CCPA 1948); In re Scherl 70 USPQ 204 (CCPA 1946); In re Irmscher 66 USPQ 314 (CCPA 1945); In re Norman 66 USPQ 308 (CCPA 1945); In re Swenson 56 USPQ 372 (CCPA 1942); In re Sola 25 USPQ 433 (CCPA 1935); In re Dreyfus 24 USPQ 52 (CCPA 1934).
Regarding claims 5 and 19, Eversen et al. and Englekirk et al. disclose the method further including configuring the plurality of substrate contacts into at least a first group and a second group of one or more substrate contacts, and configuring the at least first group and second group of one or more substrate contacts to selectively impose at least two different back bias voltages to corresponding different regions of the substrate [0014]-[0015], [0035]-[0036], and [0039].
Regarding claims 6, 13, and 20, Eversen et al. and Englekirk et al. disclose the method further including:
(a) linearly arraying the plurality of series-coupled MOSFETs on the substrate;
(b) offsetting the groups of one or more substrate contacts and the resistors to a side of the MOSFETs; and
(c) arraying and aligning the groups of one or more substrate contacts and the resistors in a direction of radio frequency signal flow through the MOSFETs.
Regarding claim 8, Iversen et al. discloses, as shown in Figures 2-4, a method of fabricating a radio frequency switch including:
fabricating a plurality of series-coupled MOSFETs (32,76) on a silicon-on-insulator substrate [0030] and configured to be coupled to a radio frequency input signal (42);
fabricating a back-bias network including:
a plurality of groups, each group comprising one or more contact (B), each contact having a first end in on a region of the substrate, and having a second end accessible to connections in a superstructure (64) of the integrated circuit;
at least one resistor (Rb), each resistor coupled to the second end of the contacts of a pair of groups and configured to provide substantial radio frequency isolation between the pair of groups.
Iversen et al. does not disclose the plurality of contacts being the substrate contacts, each substrate contact having a first end in close enough proximity to the substrate to impose a back bias voltage on a region of the substrate sufficient to increase the power handing capability of at least one of the MOSFETs. However, Englekirk et al. discloses a method of fabricating an integrated circuit including forming a plurality of contacts (1302a,1302b) being the substrate contacts, each substrate contact having a first end in close enough proximity to a substrate (402). Note Figures of Englekirk et al. Therefore, it would have been obvious to one of ordinary skills in the art at the time the invention was made to form the plurality of contact of Iversen et al. being the substrate contacts in close proximity to the substrate, such as taught by Englekirk et al. in order to further improve the power handling capability of the MOSFETs.
Regarding claim 14, Iversen et al. discloses, as shown in Figures 2-4, a method of fabricating a back-bias network configured to be coupled to a stack of series-coupled MOSFETs (32,76) fabricated as an integrated circuit on a substrate [0030], the method including:
fabricating a plurality of series-coupled MOSFETs (32,76) on a silicon-on-insulator substrate [0030] and configured to be coupled to a radio frequency input signal (42);
fabricating a plurality of groups of more than one contact (B) position within theintegrated circuit, each contact having a first end in on a region of the substrate, and having a second end accessible to connections in a superstructure (64) of the integrated circuit;
a resistive ladder (Rb,Rb,Rb) within the integrated circuit, the resistive ladder including a plurality of resistors (Rb) each coupled between respective groups of more than one contact, the resistive ladder being configured to be coupled to a bias voltage source.
Iversen et al. does not disclose the plurality of contacts being the substrate contacts, each substrate contact includes a conductive structure extending from a super structure of the integrated circuit through an active layer and an insulating buried oxide layer of the integrated circuit to or near to the substrate. However, Englekirk et al. discloses a method of fabricating an integrated circuit including plurality of contacts (1302a,1302b) being the substrate contacts, each substrate contact includes a conductive structure (1302a,1302b) extending through an active layer (408, Si layer) and an insulating buried oxide layer (BOX, 406) of the integrated circuit to or near to the substrate (402). Note Figures of Englekirk et al. to impose a back bias voltage on a region of the substrate sufficient to increase the power handing capability of at least one of the MOSFETs. Note Figures of Englekirk et al. Therefore, it would have been obvious to one of ordinary skills in the art at the time the invention was made to form the plurality of contact of Iversen et al. being the substrate contacts includes a conductive structure extending from a super structure of the integrated circuit through an active layer and an insulating buried oxide layer of the integrated circuit to or near to the substrate, such as taught by Englekirk et al. in order to further improve the power handling capability of the MOSFETs.
Regarding claim 15, Eversen et al. and Englekirk et al. disclose the method further including fabricating the resistive ladder within the superstructure (64) of the integrated circuit.
Claim(s) 7 and 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Iversen et al. (US 2013/0278317) in view of Englekirk et al. (US 2018/0337146) and further in view of Sahara et al. (US 2002/0180041).
Iversen et al. and Englekirk et al. disclose the claimed invention including the method as explained in the above rejection. Iversen et al. and Englekirk et al. do not disclose the method including providing the integrated circuit with a die seal having at least one gap having an interior, further including positioning at least one of the plurality of substrate contacts within the interior of the die seal adjacent to and overlapping at least one gap. However, Sahara et al. discloses a method including providing the integrated circuit with a die seal (9) having at least one gap (at locations that the bumps (7) are formed) having an interior, further including positioning at least one of the plurality of contacts (8) within the interior of the die seal adjacent to and overlapping at least one gap. Note Figures of Sahara et al. Therefore, it would have been obvious to one of ordinary skills in the art at the time the invention was made to form the integrated circuit of Iversen et al. and Englekirk et al. including a die seal having at least one gap having an interior, further including positioning at least one of the plurality of substrate contacts within the interior of the die seal adjacent to and overlapping at least one gap, such as taught by Sahara et al. in order to protect the integrated circuit from external contamination.
Conclusion
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/HUNG K VU/ Primary Examiner, Art Unit 2897
