DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are pending for examination.
This Office Action is Non-Final.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 6, 9, 12, and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 11256563 B2, hereinafter “Lee”) in view of Kim et al. (US 20210133028 A1, hereinafter “Kim”).
Regarding Claim 1, Lee discloses a memory device (Fig. 3 and Col 8, line 40: memory system 300) comprising:
a memory subsystem… (Fig. 3: memory device 320 is interpreted as a memory subsystem. Memory device 320 also contains memory cell array 321); and
a controller coupled to the memory subsystem (Fig. 3 and Col 8, line 45: memory controller 310 is coupled to memory device 320), the controller to control storage of user data (Col 9, lines 45-47, 49-52, 60-62: exemplary embodiments of a memory controller (such as memory controller 310) may perform a write operation from a host with respect to a first row of a memory cell array. The data written to the first row as request by the host is interpreted as “user data”), the controller having one or more caches structurally integrated within the controller (Fig. 3 and Col 8, lines 46-49: although cache memory 330 is depicted outside controller 310, memory system 300 may be implemented such that cache memory 330 is located within memory controller 310) …, the one or more caches dedicated to repair replacement and separate from the memory subsystem (Col 9, lines 45-47 and Col 10, lines 60-66: exemplary embodiments of cache memory (such as cache memory 330) may store repaired data of the faulty row (Col 5, lines 15-22: data “DATA” is a faulty row. Col 8, lines 58-64: DATA initially stored in R_Data such as R_Data of memory cell array 321), replacing the faulty row initially stored in memory cell array 321 when later requested by the host (also see Col 9, lines 2-6: replaces data stored in memory device 320, and thus replaces memory cell array 321, according to a cache hit). Therefore, cache memory 330 is dedicated to repair replacement of a faulty row initially stored in memory cell array 321. Fig. 3 and Col 8, lines 46-49: cache memory 330 may be implemented memory controller 310, which is separate from memory device 320), the controller arranged to use the one or more caches to provide resource replacement to the memory subsystem (Fig. 3; Col 8, lines 65-67; and Col 9, lines 1-6: memory controller 310 containing cache access circuit 311 uses cache memory 330 to replace memory in memory device 320 according to a cache hit)… wherein the controller is configured to, in response to a repair trigger based on a set of collected correctable error events, allocate a cache entry in the one or more caches for a failing row in the memory subsystem and move data related to the failing row to the allocated cache entry (Col 5, lines 15-48; Col 10, lines 20-44: read-requested row (Fig. 3; Col 62-64: the row originates from DATA of memory cell array 321) determined as faulty from 2-bit error detection via PAR_ECC + PAR_CRC (collected correctable error events). Col 10, lines 49-62: in response to the fault determination, the row is repaired and stored in the cache memory. 2-bit error detection triggers a repair and a cache entry is effectively allocated to store the repaired row)
Lee does not disclose:
…having multiple individual memory media
…and one or more decoders/encoders integrated within the controller, …
…the one or more caches arranged in one or more data paths with the one or more decoders/encoders to the memory subsystem based on virtual repair or physical repair.
However, Kim teaches:
a memory subsystem having multiple individual memory media (Fig. 1: memory module 180 containing memory devices 200a-td)
…and one or more decoders/encoders integrated within the controller (Fig. 2 and [0054]: memory controller 50 contains ECC 100, which contains ECC encoder 110 and ECC decoder 140), …
…the one or more caches arranged in one or more data paths with the one or more decoders/encoders to the memory subsystem (Fig. 1-2: cache 80 shown connected to ECC engine 100 containing ECC encoder 110 and ECC decoder 140 through various buses/data paths, ECC engine 100 shown further connected to memory module 180 in more data paths) based on virtual repair or physical repair (Fig. 2 and [0054]: cache 80 is arranged with ECC engine 100 containing ECC encoder 110 and ECC decoder 140. [0055] and [0057]-[0058]: cache 80 provides user data to ECC encoder 110 for codeword generation. ECC decoder 140 also performs error detection and correction on a second message including the generated codeword. Therefore, the arrangement of cache 80 with ECC encoder 110 and ECC decoder 140 enables data error correction, a type of virtual repair).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine Lee and Kim by implementing the ECC engine alongside a cache within a controller taught by Kim. One of ordinary skill in the art would be motivated to make this modification in order to provide a plurality of ECCs having different error correction capabilities (Kim: [0059]).
Regarding Claim 6, Lee in view of Kim teaches the memory device of claim 1, as referenced above, wherein the one or more caches include one or more static random-access memories (Lee: Col 8, lines 7-9: memory controller may include cache memory containing SRAM).
Regarding Claim 9, Lee discloses a method of operating a memory device (Fig. 3 and Fig. 5: system 300 interpreted as a memory device), the method comprising:
in response to a repair trigger, allocating in a cache dedicated to repair replacement (Col 9, lines 45-47 and Col 10, lines 60-66: exemplary embodiments of cache memory (such as cache memory 330) may store repaired data of the faulty row (Col 5, lines 15-22: data “DATA” is a faulty row. Col 8, lines 58-64: DATA initially stored in R_Data such as R_Data of memory cell array 321), replacing the faulty row initially stored in memory cell array 321 when later requested by the host (also see Col 9, lines 2-6: replaces data stored in memory device 320, and thus replaces memory cell array 321, according to a cache hit). Therefore, cache memory 330 is dedicated to repair replacement of a faulty row initially stored in memory cell array 321) and structurally integrated within a controller of the memory device (Fig. 3 and Col 8, lines 46-49: although cache memory 330 is depicted outside controller 310, memory system 300 may be implemented such that cache memory 330 is located within memory controller 310), a cache entry for a failing row, the failing row being in memory media of the memory device (Fig. 5, S24-25 and Col 10, lines 34-52: detection of a faulty row triggers a recovery algorithm to repair the row. Col 10, lines 60-63: the repaired row may be stored in the cache, which is known by one of ordinary skill in the art to encompass allocating a cache entry in order to store the row. Col 5, lines 15-22: describes data DATA as a faulty row. Col 8, lines 58-64: data DATA initially stored in R_Data such as R_Data of memory cell array 321 within system 300. Thus, the faulty row is a row in array 321 of system 300), the memory media being separate from the controller (Fig. 3: memory cell array 321 shown separate from memory controller 310)…; and
moving data related to the failing row to the cache in accordance with the allocated cache entry (Col 10, lines 60-63: the repaired row may be moved to cache, which was previously described to encompass moving the repaired row in an allocated cache entry).
Lee does not disclose:
the cache arranged with one or more decoders/encoders integrated within the controller in one or more data paths to the memory media
However, Kim teaches:
the cache arranged with one or more decoders/encoders integrated within the controller in one or more data paths to the memory media (Fig. 1-2: cache 80 shown connected to ECC engine 100 containing ECC encoder 110 and ECC decoder 140 through various buses/data paths, ECC engine 100 shown further connected to memory module 180 in more data paths)
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine Lee and Kim by implementing the ECC engine alongside a cache within a controller taught by Kim. One of ordinary skill in the art would be motivated to make this modification in order to provide a plurality of ECCs having different error correction capabilities (Kim: [0059]).
Regarding Claim 12, Lee in view of Kim the method of claim 9, as referenced above, wherein the method includes responding to the repair trigger based on a set of collected correctable error events (Lee: Fig. 5, S22-S26 and Col 10, lines 25-58: Examiner interprets “responding to the repair trigger based on a set of collected correctable error events” as the set of collected correctable error events (i.e., ECC and CRC parity error detection) triggers a repair, and a response merely follows the trigger (i.e., the recovery algorithm)).
Regarding Claim 15, Lee in view of Kim teaches the method of claim 9, as referenced above, wherein allocating the cache entry includes allocating the cache entry in one or more static random-access memories in the controller dedicated to repair replacement (Lee: Col 8, lines 7-9: memory controller may further include cache memory containing SRAM. Col 10, lines 60-63: one of ordinary skill in the art would understand a cache entry was allocated to store the repaired row. Col 10, lines 62-66: the cached data replaces the original faulty row. Therefore, the cache entry is dedicated to the repaired row and replaces the original row).
Claims 2-5 are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Kim, and in further view of Wilson et al. (US 20220291854 A1, hereinafter “Wilson”).
Regarding Claim 2, Lee in view of Kim teaches the memory device of claim 1, as referenced above, wherein the memory subsystem has one or more memory media (Lee: Fig. 3: memory device 320 contains memory cell array 321) and the controller is configured to process user data with the one or more memory media sharing the one or more caches (Lee: Col 9, lines 45-47, 49-52, 60-62: exemplary embodiments of a memory controller (such as memory controller 310) may perform a write operation from a host with respect to a first row of a memory cell array. The data written to the first row as request by the host is interpreted as “user data.” Fig. 3 and Col 8, lines 65-67: data read from memory device 320 (e.g., from memory cell array 321) may be stored in cache memory 330, therefore memory cell array 321 shares cache memory 330),
Lee in view of Kim does not teach:
the controller having an individual decoder/encoder for each memory medium of the one or more memory media, with the individual decoders/encoders configured between the one or more caches and the one or more memory media.
However, KHAN discloses teaches
the controller having an individual decoder/encoder for each memory medium of the one or more memory media (Fig. 1: controller 150 contains encoder/decoders 152-158 for volatile array), with the individual decoders/encoders configured between the one or more caches and the one or more memory media (Fig. 1: encoders/decoders 152-158 are configured between cache 142 and volatile array 144).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to implement the encoders/decoders taught by KHAN into the controller taught by Lee in view of Kim. One of ordinary skill in the art would be motivated to make this modification in order to provide on-die internal error checking and correction (KHAN: [0003]).
Regarding Claim 3, Lee in view of Kim the memory device of claim 1, as referenced above, wherein…. the controller… is configured to process user data (Lee: Col 9, lines 45-47, 49-52, 60-62: exemplary embodiments of a memory controller (such as memory controller 310) may perform a write operation from a host with respect to a first row of a memory cell array. The data written to the first row as request by the host is interpreted as “user data”)
Lee in view of Kim does not teach:
wherein the memory subsystem has multiple individual memory media, the controller has an individual decoder/encoder for each individual memory medium of the multiple individual memory media, the controller has multiple caches and… with each memory medium of the multiple individual memory media allocated to an individual cache of the multiple caches and with each individual decoder/encoder configured between a corresponding allocated cache and the individual memory medium corresponding to the individual decoder/encoder.
However, KHAN teaches: wherein the memory subsystem has multiple individual memory media (Fig. 1: system 100 includes volatile array 144 and nonvolatile array 164), the controller has an individual decoder/encoder for each individual memory medium of the multiple individual memory media (Fig. 1: Examiner interprets “controller” as memory controller 120, including memory bus 122, volatile DIMM 140, nonvolatile DIMM 160, and all components within each DIMM. Encoders/decoders are paired with each array), the controller has multiple caches (Fig. 1: cache 142 and 162) and… with each memory medium of the multiple individual memory media allocated to an individual cache of the multiple caches (Fig. 1: volatile array 144 is paired with cache 142. Nonvolatile array 164 is paired with cache 162) and with each individual decoder/encoder configured between a corresponding allocated cache and the individual memory medium corresponding to the individual decoder/encoder (Fig. 1: encoders/decoders 152-158 are configured between cache 142 and volatile array 144. Encoders 172-178 are configured between cache 162 and nonvolatile array 164).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to implement the encoders/decoder arrangement taught by KHAN into the memory controller taught by Lee in view of Kim. One of ordinary skill in the art would be motivated to make this modification in order to provide on-die internal error checking and correction (KHAN: [0003]).
Regarding Claim 4, Lee in view of Kim teaches the memory device of claim 1, as referenced above, wherein the memory subsystem has one or more memory media (Lee: Fig. 3: memory device 320 contains memory cell array 321) and the controller is configured to process user data with the one or more memory media sharing the one or more caches (Lee: Col 9, lines 45-47, 49-52, 60-62: exemplary embodiments of a memory controller (such as memory controller 310) may perform a write operation from a host with respect to a first row of a memory cell array. The data written to the first row as request by the host is interpreted as “user data.” Fig. 3 and Col 8, lines 65-67: data read from memory device 320 (e.g., from memory cell array 321) may be stored in cache memory 330, therefore memory cell array 321 shares cache memory 330).
Lee in view of Kim does not teach:
the controller having an individual decoder/encoder for each memory medium of the one or more memory media, with the one or more caches configured between the individual decoders/encoders and the one or more memory media.
However, KHAN discloses:
the controller having an individual decoder/encoder for each memory medium of the one or more memory media (Fig. 1: controller 150 contains encoder/decoders 152-158 for volatile array 144), with the one or more caches configured between the individual decoders/encoders and the one or more memory media (cache 142 is configured between encoders/decoders 152-158 and volatile array 144).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to implement the encoders/decoders taught by KHAN into the memory controller taught by Lee in view of Kim. One of ordinary skill in the art would be motivated to make this modification in order to provide on-die internal error checking and correction (KHAN: [0003]).
Regarding Claim 5, Lee in view of Kim teaches the memory device of claim 1, as referenced above.
Lee in view of Kim does not teach:
wherein the memory subsystem has multiple individual memory media, and the controller includes: an individual decoder and individual encoder for each individual memory medium of the multiple individual memory media; and multiple caches, each cache of the multiple caches allocated to an individual memory medium of the multiple individual memory media, with each allocated cache configured between the individual memory medium and each individual decoder and individual encoder corresponding to the individual memory medium.
However, KHAN teaches:
wherein the memory subsystem has multiple individual memory media (Fig. 1: system 100 contains volatile array 144 and nonvolatile array 164), and the controller (Fig. 1: controller is interpreted as memory controller 120 and all components within DIMMs 140 and 160) includes:
an individual decoder and individual encoder for each individual memory medium of the multiple individual memory media (Fig. 1: each DIMM in memory controller 120 contains encoders/decoders for their corresponding arrays); and multiple caches, each cache of the multiple caches allocated to an individual memory medium of the multiple individual memory media (Fig. 1: caches 142 and 162 are allocated to volatile array 144 and nonvolatile array 164, respectively), with each allocated cache configured between the individual memory medium and each individual decoder and individual encoder corresponding to the individual memory medium (Fig. 1: within each DIMM, the cache is configured between encoders/decoders and memory array. Each encoder/decoder are paired with their respective array).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to implement the encoders/decoders taught by KHAN into the memory controller taught by Lee in view of Kim. One of ordinary skill in the art would be motivated to make this modification in order to provide on-die internal error checking and correction (KHAN: [0003]).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Kim, and in further view of Kerstetter (US 20230350574 A1, hereinafter “Kerstetter”).
Regarding Claim 7, Lee in view of Kim teaches the memory device of claim 1, as referenced above.
Lee in view of Kim does not teach:
wherein the controller is an application-specific integrated circuit.
However, Kerstetter teaches:
wherein the controller is an application-specific integrated circuit ([0044]: Memory sub-system controller 115 can be an ASIC).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to substitute the memory controller taught by Lee in view of Kim with the memory sub-system controller taught by Kerstetter. One of ordinary skill in the art would be motivated to make this modification because a simple substitution of one known element (Lee: Fig. 3: memory controller 310) for another (Kerstetter: ASIC memory subsystem controller 115) to obtain predictable results (Kerstetter: a memory controller for reading, writing, and storing data). See MPEP 2143(I)(B).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Kim, in further view of Chen et al. (US 20090282305 A1, hereinafter “Chen”).
Regarding Claim 8, Lee in view of Kim teaches the memory device of claim 1, as referenced above, wherein the repair trigger is based on the set of collected correctable error events… (Lee: Col 5, lines 15-48; Col 10, lines 20-44: read-requested row (Fig. 3; Col 62-64: the row originates from DATA of memory cell array 321) determined as faulty from 2-bit error detection via PAR_ECC + PAR_CRC (collected correctable error events). Col 10, lines 49-62: in response to the fault determination, the row is repaired and stored in the cache memory. 2-bit error detection triggers a repair)
Lee in view of Kim does not teach:
…in conjunction with specified tests performed at run time
However, Chen teaches:
wherein the repair trigger is based on… specified tests performed at run time (Abstract: test data recovery procedure by writing test data into a memory block where error data is found, finding an error bit by reading the test data, and reducing the error to a recoverable range of the ECC technique)
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine Lee, Kim, and Chen by performing a simple substitution of one known element (Lee: Col 6, lines 20-52: arbitrary host read request for data of a first row to cause an error detection operation to be performed performed via collected correctable error events ECC + CRC parity, determines a faulty row, and triggers a recovery algorithm) for another (Chen: read request for generated test data) to obtain predictable results (read request for faulty data, detecting errors in read data, and recovering the data).
Claims 10-11 are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Kim, in further view of Goodman (US 20120311248 A1).
Regarding Claim 10, Lee in view of Kim teaches the method of claim 9, as referenced above.
Lee in view of Kim does not teach:
wherein read commands related to the failing row are put on hold until the moving of the data is completed.
However, Goodman teaches:
wherein read commands related to the failing row are put on hold until the moving of the data is completed ([0032] Once the write of the corrected data to the cache is complete, all read operations to the address of the failing memory location will use the data from the LL cache 208. Examiner interprets “put on hold” as requiring all read operations to use the corrected data from LL cache 208. Therefore, the failing memory must be moved first before read operations may occur).
Therefore, it would have been obvious before the effective filing data of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine Lee, Kim, and Goodman by utilizing the corrected data in cache as taught by Goodman. One of ordinary skill in the art would be motivated to make this modification because the cached data is guaranteed to be reliable since it is line locked, and does not require additional hardware or software for tracking and/or accessing the corrected data (Goodman: [0032]).
Regarding Claim 11, Lee in view of Kim teaches the method of claim 9, as referenced above.
Lee in view of Kim does not teach:
wherein write commands related to the failing row are accepted and data is stored in the cache.
However, Goodman teaches:
wherein write commands related to the failing row are accepted and data is stored in the cache ([0032] All write operations to the address of the failing memory location will use the data from the LL cache 208. [0029] and [0031]: the LL cache 208 data refers to the corrected data of faulty memory element(s) in DRAM 212, now stored in spare cache memory).
Therefore, it would have been obvious before the effective filing data of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine Lee, Kim, and Goodman by utilizing the corrected data in cache as taught by Goodman. One of ordinary skill in the art would be motivated to make this modification because the cached data is guaranteed to be reliable since it is line locked, and does not require additional hardware or software for tracking and/or accessing the corrected data (Goodman: [0032]).
Claims 13-14 and 16-20 are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view Kim, in further view of of Das et al. (US 20170185473 A1, hereinafter “Das”).
Regarding Claim 13, Lee in view of Kim teaches the method of claim 9, as referenced above.
Lee in view of Kim does not teach:
wherein moving data includes storing error correction code data in the cache.
However, Lee in view Kim, in further view of Das teaches:
wherein moving data includes storing error correction code data in the cache (Lee: Col 5, lines 15-22: parities PAR_ECC and PAR_CRC are used to determine a faulty row. Das: Fig. 2 and [0028]: upon detecting the error at the location of the cache line 200, parity data 204 may be written and stored in the cache line 200).
Therefore, it would have been obvious before the effective filing data of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine Lee and Kim with Das by expanding upon writing parity information to the cache as shown in Das by writing the ECC parity taught by Lee. One of ordinary skill in the art would be motivated to make this modification to provide error detection at the cache line (Das: [0028]).
Regarding Claim 14, Lee in view of Kim teaches the method of claim 9, as referenced above.
Lee in view of Kim does not teach:
wherein the method includes storing parity information in the cache.
However, Das teaches:
wherein the method includes storing parity information in the cache (Das: Fig. 2 and [0028]: upon detecting the error at the location of the cache line 200, parity data 204 may be written and stored in the cache line 200).
Therefore, it would have been obvious before the effective filing data of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine Lee and Kim with Das by implementing the parity writing taught by Das. One of ordinary skill in the art would be motivated to make this modification to provide error detection at the cache line (Das: [0028]).
Regarding Claim 16, Lee discloses a method of operating a memory device (Fig. 3 and Fig. 5, wherein system 300 is interpreted to be a memory device), the method comprising:
in response to a repair trigger, allocating, in a cache dedicated to repair replacement (Col 9, lines 45-47 and Col 10, lines 60-66: exemplary embodiments of cache memory (such as cache memory 330) may store repaired data of the faulty row (Col 5, lines 15-22: data “DATA” is a faulty row. Col 8, lines 58-64: DATA initially stored in R_Data such as R_Data of memory cell array 321), replacing the faulty row initially stored in memory cell array 321 when later requested by the host (also see Col 9, lines 2-6: replaces data stored in memory device 320, and thus replaces memory cell array 321, according to a cache hit). Therefore, cache memory 330 is dedicated to repair replacement of a faulty row initially stored in memory cell array 321) and structurally integrated within a controller of the memory device (Fig. 3 and Col 8, lines 46-49: although cache memory 330 is depicted outside controller 310, memory system 300 may be implemented such that cache memory 330 is located within memory controller 310), a cache entry for a failing row, the failing row being in memory media of the memory device (Fig. 5, S24-25 and Col 10, lines 34-52: detection of a faulty row triggers a recovery algorithm to repair the row. Col 10, lines 60-63: the repaired row may be stored in the cache, which is known by one of ordinary skill in the art to encompass allocating a cache entry in order to store the row. Col 5, lines 15-22: describes data DATA as a faulty row. Col 8, lines 58-64: data DATA initially stored in R_Data such as R_Data of memory cell array 321 within system 300. Thus, the faulty row is a row in array 321 of system 300) separate from the controller (Fig. 3: memory cell array 321 shown separate from memory controller 310)…; and
…a last column of data related to the failing row… the last column of data being data that triggered the repair (Fig. 3 and Col 58-64: ECC_PAR and CRC_PAR are stored in R_Par, a last column for all R_Data rows in memory cell array 321. Fig. 5 and Col 10, lines 34-58: ECC and CRC parity determines whether the row has a fault in S24, and if so, triggers a recovery algorithm to repair the row in S25-26)
Lee does not disclose:
the cache arranged with one or more decoders/encoders integrated within the controller in one or more data paths to the memory media
writing a last column of data related to the failing row to the cache…
However, Kim teaches:
the cache arranged with one or more decoders/encoders integrated within the controller in one or more data paths to the memory media (Fig. 1-2: cache 80 shown connected to ECC engine 100 containing ECC encoder 110 and ECC decoder 140 through various buses/data paths, ECC engine 100 shown further connected to memory module 180 in more data paths)
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine Lee and Kim by implementing the ECC engine alongside a cache within a controller taught by Kim. One of ordinary skill in the art would be motivated to make this modification in order to provide a plurality of ECCs having different error correction capabilities (Kim: [0059]).
Lee in view of Kim does not teach:
writing a last column of data related to the failing row to the cache…
However, Das teaches:
writing a last column of data related to the failing row to the cache (Fig. 2 and [0028]: upon detecting the error at the location of the cache line 200, shown as a row, parity data 204 may be written and stored in the cache line 200. Parity data 204 is shown to be the last column in cache line 200)
Therefore, it would have been obvious before the effective filing data of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine Lee and Kim with Das by writing parity information in the cache as taught by Das alongside the repaired data taught by Lee. One of ordinary skill in the art would be motivated to make this modification to provide error detection within the cache line (Das: [0028]).
Regarding Claim 17, Lee in view Kim, in further view of Das discloses the method of claim 16, as referenced above, wherein the method includes inserting data of another column related to the failing row into the cache upon request from a host initiating the writing of the data (Lee: Fig. 3 and Col 8, lines 58-64: Examiner interprets “another column” as data DATA from R_Data in memory array 321. Col 10, lines 20-21: A host initiates a read request of a first data row. Col 10, lines 49-63: after determining the row is faulty and repairing the row, the repaired data is stored in the cache. Therefore, the host read request initiates writing of the faulty row from column R_data to cache memory).
Regarding Claim 18, Lee in view Kim, in further view of Das discloses the method of claim 17, as referenced above, wherein the method includes, if the other column is not listed in the cache, inserting data of the other column in the cache from the memory media in a backend process (Lee: Fig. 11, S33 and Col 15, lines 31-33: Examiner interprets updating write data in cache memory as inserting a version of write data not currently listed in cache memory. Col 8, lines 57-64 and Col 9, lines 11-24: write data to cache memory includes DATA from R_Data of memory cell array 321 (previously described to be “the other column” – see above). Writing DATA occurs while an update operation takes place, thus writing DATA is performed in a backend process relative to the update operation).
Regarding Claim 19, Lee in view of Kim, in further view of Das discloses the method of claim 16, as referenced above, wherein allocating the cache entry includes allocating the cache entry in a cache dedicated to repair replacement (Lee: Col 10, lines 60-63: an entry in the cache is allocated to storing the repaired row. Col 10, lines 62-66: the cached data replaces the original faulty row. Therefore, the cache entry is dedicated to the repaired row and replaces the original row).
Regarding Claim 20, Lee in view of Kim, in further view of Das discloses the method of claim 19, as referenced above, wherein the cache is one or more static random-access memories in the controller (Lee: Col 8, lines 7-9: memory controller may further include cache memory containing SRAM).
Response to Arguments
Applicant's arguments filed 02/18/2026 have been fully considered but they are not persuasive.
Applicant argues:
“The cache of Lee is not dedicated to repair replacement. From the quotes above (not included, see Page 7-8 of Applicant Remarks), it is clear that the cache of Lee is not dedicated to repair replacement but rather to reducing frequency access to the memory… It appears that Lee has caches in the systems that can be used, among other things, to provide reliability.”
Lee / Lee in view of Kim does not disclose the amended limitations regarding encoders/decoders
Examiner respectfully disagrees.
Regarding A, Merriam-Webster Dictionary defines “dedicate to” (phrasal v.) as “to decide that (something) will be used for (a special purpose).” As cited above and in Lee: Col 10, lines 49-66; the cache memory is used to store repaired data so that the host does not have to perform an error detection and recovery algorithm. Thus, the cache memory is used for the special purpose of storing repaired data. Under BRI, “dedicated to” is not limited to “solely dedicated to a single use and a single use only.” Rather, “dedicated” also encompasses merely used for a special purpose and may be used along with other special purposes. Therefore, the 103 rejections under Lee (and dependent on Lee) are maintained.
Regarding B, Kim teaches the amended limitations regarding encoders/decoders as cited above.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CATHERINE MARIE NGUYEN whose telephone number is (571)272-6160. The examiner can normally be reached M-F 7:30 AM - 4:30 PM ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, ASHISH THOMAS can be reached at (571) 272-0631. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/C.M.N./Examiner, Art Unit 2114
/ASHISH THOMAS/Supervisory Patent Examiner, Art Unit 2114