DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Email Communication
Applicant is encouraged to authorize the Examiner to communicate with applicant via email by filing form PTO/SB/439 either via USPS, Central Fax, or EFS-Web. See MPEP 502.01, 502.03, 502.05.
Election/Restrictions
Claim(s) 19-23 is/are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 29 April 2026.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 112
Claim(s) 18 is/are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 18 recites the limitation "wherein the first dummy pattern is disposed to overlap a region in which the first internal electrode is spaced apart from the fifth and sixth surfaces and a space in which the first-first internal pattern and the first-second internal pattern are spaced apart from each other, and
the second dummy pattern is disposed to overlap a space in which the second internal electrode is spaced apart from the third to sixth surfaces”. There is insufficient antecedent basis for this limitation in the claim. For the purpose of examination, the examiner is taking “wherein the first dummy pattern is disposed to overlap a region in which the first internal electrode is spaced apart from the fifth and sixth surfaces and a space in which the first-first internal pattern and the first-second internal pattern are spaced apart from each other, and the second dummy pattern is disposed to overlap a space in which the second internal electrode is spaced apart from the third to sixth surfaces” to read “wherein the first margin pattern is disposed to overlap a region in which the first internal electrode is spaced apart from the fifth and sixth surfaces and a space in which the first-first internal pattern and the first-second internal pattern are spaced apart from each other, and the second margin pattern is disposed to overlap a space in which the second internal electrode is spaced apart from the third to sixth surfaces”.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-7, 12-14, & 17 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hirai (US 2023/0268119).
In regards to claim 1, Hirai ‘119 discloses
A multilayer electronic component, comprising:
a body (12 – fig. 1; [0026]) including a plurality of dielectric layers (14 – fig. 2; [0027]), a first internal electrode (16a – fig. 2; [0060]), a second internal electrode (16b – fig. 2; [0060]), and a margin pattern (40a-40d – fig. 3-4; [0041-0042]); and
an external electrode (30a -30b – fig. 1; [0066]) disposed on the body,
wherein the first and second internal electrodes are alternately disposed in a first direction with the dielectric layer interposed therebetween (fig. 2), and
the margin pattern is disposed in a position different from the first and second internal electrodes in the first direction and is disposed so as not to overlap the first internal electrode or the second internal electrode in the first direction (fig. 3-4 & 6).
In regards to claim 2, Hirai ‘119 discloses
The multilayer electronic component according to claim 1, wherein the margin pattern includes a first margin pattern (40a/0b – fig. 4) disposed so as not to overlap the first internal electrode in the first direction and a second margin pattern (40c/40d – fig. 4) disposed so as not to overlap the second internal electrode in the first direction, and
the first margin pattern and the second margin pattern are alternately disposed in the first direction.
In regards to claim 3, Hirai ‘119 discloses
The multilayer electronic component according to claim 2, wherein the body has first and second surfaces (12a & 12b – fig. 1; [0027]) opposing each other in the first direction, third and fourth surfaces (12e & 12f – fig. 1; [0027]) connected to the first and second surfaces and opposing each other in a second direction, and fifth and sixth surfaces (12c & 12d – fig. 1; [0027]) connected to the first to fourth surfaces and opposing each other in a third direction (fig. 1).
In regards to claim 4, Hirai ‘119 discloses
The multilayer electronic component according to claim 3, wherein the first internal electrode is connected to the third surface and is spaced apart from the fourth, fifth and sixth surfaces (fig. 3-4), the second internal electrode is connected to the fourth surface and is spaced apart from the third, fifth and sixth surfaces (fig. 3-4), and the first and second margin patterns are spaced apart from the third to sixth surfaces (fig. 3-4).
In regards to claim 5, Hirai ‘119 discloses
The multilayer electronic component according to claim 4, wherein, when viewed in the first direction, a separation distance between the first internal electrode and the first margin pattern is 30 µm or less, and a separation distance between the second internal electrode and the second margin pattern is 30 µm or less (fig. 4; table 1 – sample 13 – Wgap is 91 µm and Wp is 81.9 µm thus the separation has to be less than 9.1).
In regards to claim 6, Hirai ‘119 discloses
The multilayer electronic component according to claim 4, wherein, when viewed in the first direction, a separation distance between the first internal electrode and the first margin pattern is 0.5 µm or more and 30 µm or less, and a separation distance between the second internal electrode and the second margin pattern is 0.5 µm or more and 30 µm or less (fig. 4; table 1 – sample 13 – Wgap is 91 µm and Wp is 81.9 µm thus the separation will be less than 9.1 µm; furthermore the margin pattern is shown centered in the gap and thus the separation will be ~4.5 µm).
In regards to claim 7, Hirai ‘119 discloses
The multilayer electronic component according to claim 3, wherein the first and second margin patterns are spaced apart from the third to sixth surfaces by a distance of 15 µm or more (fig. 3 & 5; table 1 – sample 13 – LP is 360 µm and Lm is 1500 µm furthermore the margin pattern is shown centered in the gap and thus the spacing will be ~570 µm).
In regards to claim 12, Hirai ‘119 discloses
The multilayer electronic component according to claim 4, wherein, a region in which the first internal electrode is spaced apart from the fifth surface is referred to as a first-first width margin, a region spaced apart from the sixth surface is referred to as a first-second width margin, and a region in which the first internal electrode is spaced apart from the fourth surface is referred to as a first length margin (fig. 4-6; table 1 – sample 10), and
the first margin pattern is disposed to overlap one of the first-first and first-second width margins and the first length margin in the first direction (fig. 4-6; table 1 – sample 10).
In regards to claim 13, Hirai ‘119 discloses
The multilayer electronic component according to claim 4, wherein, a region in which the first internal electrode is spaced apart from the fifth and sixth surfaces is referred to as a first width margin, a region in which the first internal electrode is spaced apart from the fourth surface is referred to as a first length margin, a region in which the second internal electrode is spaced apart from the fifth and sixth surfaces is referred to as a second width margin, and a region in which the second internal electrode is spaced apart from the third surface is referred to as a second length margin (fig. 3-4 & 6), and
the first and second margin patterns are disposed to overlap the first and second width margins, and are disposed so as not to overlap the first and second length margins (fig. 3-4 & 6).
In regards to claim 14, Hirai ‘119 discloses
The multilayer electronic component according to claim 1, wherein the margin pattern is comprised of a plurality of spaced apart patterns (fig. 4).
In regards to claim 17, Hirai ‘119 discloses
The multilayer electronic component according to claim 3, wherein the first internal electrode includes a first-first internal pattern (16a – fig. 7) connected to the third surface and spaced apart from the fourth, fifth and sixth surfaces, and a first-second internal pattern (16b – fig. 7) spaced apart from the first internal pattern and connected to the fourth surface and spaced apart from the third, fifth and sixth surfaces, and
the second internal electrode includes a floating pattern (16c – fig. 7; [0070]) spaced apart from the third to sixth surfaces.
Claim(s) 1-3, 8, 14, 24-25, & 29-30 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yamamoto (US 2003/0011962).
In regards to claim 1, Yamamoto discloses
A multilayer electronic component, comprising:
a body (4 – fig. 3; [0047]) including a plurality of dielectric layers (1 – fig. 1 & 5; [0047]), a first internal electrode (2 – fig. 1 & 5; [0047]), a second internal electrode (3 – fig. 1 & 5; [0073]), and a margin pattern (12a-12b and/or 13a-13b – fig. 5; [0048]); and
an external electrode (5a-5b & 6 – fig. 3; [0047]) disposed on the body,
wherein the first and second internal electrodes are alternately disposed in a first direction with the dielectric layer interposed therebetween (fig. 1 & 5), and
the margin pattern is disposed in a position different from the first and second internal electrodes in the first direction and is disposed so as not to overlap the first internal electrode or the second internal electrode in the first direction (fig. 5).
In regards to claim 2, Yamamoto discloses
The multilayer electronic component according to claim 1, wherein the margin pattern includes a first margin pattern disposed so as not to overlap the first internal electrode in the first direction and a second margin pattern disposed so as not to overlap the second internal electrode in the first direction (fig. 1 & 5), and
the first margin pattern and the second margin pattern are alternately disposed in the first direction (fig. 5).
In regards to claim 3, Yamamoto discloses
The multilayer electronic component according to claim 2, wherein the body has first and second surfaces opposing each other in the first direction, third and fourth surfaces connected to the first and second surfaces and opposing each other in a second direction, and fifth and sixth surfaces connected to the first to fourth surfaces and opposing each other in a third direction (fig. 3).
In regards to claim 8, Yamamoto discloses
The multilayer electronic component according to claim 1, wherein a first directional position of the margin pattern is disposed between a first directional position of the first internal electrode and a first directional position of the second internal electrode (fig. 5).
In regards to claim 14, Yamamoto discloses
The multilayer electronic component according to claim 1, wherein the margin pattern is comprised of a plurality of spaced apart patterns (fig. 5).
In regards to claim 24, Yamamoto discloses
A multilayer electronic component, comprising:
a body (4 – fig. 3; [0047]) including a capacitance formation portion (portion of overlap between 2 & 3) including a plurality of dielectric layers (1 – fig. 1 & 5; [0047]), a first internal electrode (2 – fig. 1 & 5; [0047]), a second internal electrode (3 – fig. 1 & 5; [0073]), and a margin pattern (12a-12b & 13a-13b – fig. 5; [0048]) including a portion disclosed in a region outside the capacitance formation portion (fig. 1 & 5); and
an external electrode (5a-5b & 6 – fig. 3; [0047]) disposed on the body,
wherein the first and second internal electrodes are alternately disposed in a first direction with the dielectric layer interposed therebetween (fig. 1 & 5), and
in the first direction, the margin pattern is disposed in a position different from the first and second internal electrodes (fig. 5).
In regards to claim 25, Yamamoto discloses
The multilayer electronic component according to claim 24, wherein the margin pattern includes a first margin pattern (12a/12b) and a second margin pattern (13a/13b), and
the first internal electrode, the first margin pattern, the second internal electrode, and the second margin pattern are alternately disposed in the first direction (fig. 5).
In regards to claim 29, Yamamoto discloses
The multilayer electronic component according to claim 25, wherein, when viewed in the first direction, the first margin pattern extends along an edge of the first internal electrode and the second margin pattern extends along an edge of the second internal electrode (fig. 2 & 5).
In regards to claim 30, Yamamoto discloses
The multilayer electronic component according to claim 24, wherein the margin pattern is comprised of a plurality of spaced apart patterns (fig. 5).
Claim(s) 1-3 & 14-16 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yoshida et al. (US 2010/0002356).
In regards to claim 1, Yoshida ‘356 discloses
A multilayer electronic component, comprising:
a body including a plurality of dielectric layers (23 – fig. 2; [0057]), a first internal electrode (32 – fig. 2; [0059]), a second internal electrode (33 – fig. 2; [0059]), and a margin pattern (uppermost and lowermost 34 & 35 – fig. 2; [0059]); and
an external electrode (30-31 – fig. 2; [0058]) disposed on the body,
wherein the first and second internal electrodes are alternately disposed in a first direction with the dielectric layer interposed therebetween (fig. 2), and
the margin pattern is disposed in a position different from the first and second internal electrodes in the first direction and is disposed so as not to overlap the first internal electrode or the second internal electrode in the first direction (fig. 2-3).
In regards to claim 2, Yoshida ‘356 discloses
The multilayer electronic component according to claim 1, wherein the margin pattern includes a first margin pattern (34) disposed so as not to overlap the first internal electrode in the first direction and a second margin pattern (35) disposed so as not to overlap the second internal electrode in the first direction, and
the first margin pattern and the second margin pattern are alternately disposed in the first direction (fig. 2).
In regards to claim 3, Yoshida ‘356 discloses
The multilayer electronic component according to claim 2, wherein the body has first and second surfaces opposing each other in the first direction, third and fourth surfaces connected to the first and second surfaces and opposing each other in a second direction, and fifth and sixth surfaces connected to the first to fourth surfaces and opposing each other in a third direction (fig. 1-3).
In regards to claim 14, Yoshida ‘356 discloses
The multilayer electronic component according to claim 1, wherein the margin pattern is comprised of a plurality of spaced apart patterns (fig. 3).
In regards to claim 15, Yoshida ‘356 discloses
The multilayer electronic component according to claim 3, wherein the first internal electrode includes a first internal pattern connected to the third surface and spaced apart from the fourth, fifth, and sixth surfaces, and a first dummy pattern (35 in plane with 32 – fig. 3) spaced apart from the first internal pattern and connected to the fourth surface and spaced apart from the third, fifth and sixth surfaces, and
the second internal electrode includes a second internal pattern connected to the fourth surface and spaced apart from the third, fifth and sixth surfaces, and a second dummy pattern (34 in plane with 33 – fig. 3) spaced apart from the second internal pattern and connected to the third surface.
In regards to claim 16, Yoshida ‘356 discloses
The multilayer electronic component according to claim 15, wherein the first margin pattern is disposed to overlap a region in which the first internal electrode is spaced apart from the fifth and sixth surfaces and a space in which the first internal pattern and the first dummy pattern are spaced apart from each other (fig. 2-3), and
the second margin pattern is disposed to overlap a region in which the second internal electrode is spaced apart from the fifth and sixth surfaces and a space in which the second internal pattern and the second dummy pattern are spaced apart from each other (fig. 2-3).
Claim(s) 24-25 & 31 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by JP2005251940A hereafter referred to as Iwasaakio.
In regards to claim 24, Iwasaakio discloses
A multilayer electronic component, comprising:
a body including a capacitance formation (overlapping portion of 2a & 2b) portion including a plurality of dielectric layers (3 – fig. 1; [0020]), a first internal electrode (2a – fig. 1; [0020]), a second internal electrode (2b – fig. 1; [0020]), and a margin pattern (11a/11b – fig. 1; [0024]) including a portion disclosed in a region outside the capacitance formation portion (fig. 1); and
an external electrode (5a/5b – fig. 1; [0020]) disposed on the body,
wherein the first and second internal electrodes are alternately disposed in a first direction with the dielectric layer interposed therebetween (fig. 1), and
in the first direction, the margin pattern is disposed in a position different from the first and second internal electrodes (fig. 1).
In regards to claim 25, Iwasaakio discloses
The multilayer electronic component according to claim 24, wherein the margin pattern includes a first margin pattern (11a) and a second margin pattern (11b), and
the first internal electrode, the first margin pattern, the second internal electrode, and the second margin pattern are alternately disposed in the first direction (fig. 1).
In regards to claim 31, Iwasaakio discloses
The multilayer electronic component according to claim 24, wherein the margin pattern and the first and second internal electrodes include a same material ([0025]).
Allowable Subject Matter
Claim(s) 9-11 & 26-28 is/are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The prior art does not teach or suggest (in combination with the other claim limitations) wherein, a region in which the first internal electrode is spaced apart from the fifth surface is referred to a first-first width margin, a region in which the first internal electrode is spaced apart from the fourth surface is referred to as a first length margin, a third directional size of the first-first width margin is referred to as WM1, a third directional size of the margin pattern overlapping the first-first width margin is referred to as WMP1, a second directional size of the first length margin is referred to as LM1, and a second directional size of the margin pattern overlapping the first length margin is referred to as LMP1, and WMP1/WM1 and LMP1/LM1 satisfy 0.33 or more and 0.54 or less (claims 9-10), wherein, when viewed from the first direction, the first margin pattern has a shape surrounding the first internal electrode, and the second margin pattern has a shape surrounding the second internal electrode (claim 11), and wherein the body has first and second surfaces opposing each other in the first direction, third and fourth surfaces connected to the first and second surfaces and opposing each other in a second direction, and fifth and sixth surfaces connected to the first to fourth surfaces and opposing each other in a third direction, the first internal electrode is connected to the third surface and is spaced apart from the fourth, fifth and sixth surfaces, the second internal electrode is connected to the fourth surface and is spaced apart from the third, fifth and sixth surfaces, and the first and second margin patterns are spaced apart from the third to sixth surfaces (claim 26-28).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
JP08316087A – fig. 1 JP03059627U – fig. 1-2
JP2000133545A – fig. 6 JP2000269074A – fig. 3
JP2005108890A – fig. 2 US 20030011963 – fig. 4
US 2026/0011493 – fig. 1-5 US 2021/0134529 – fig. 5
US 11257621 – fig. 8
Communication
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID M SINCLAIR whose telephone number is (571)270-5068. The examiner can normally be reached M-TH from 8AM-4PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, TIMOTHY J DOLE can be reached at (571)272-2229. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/David M Sinclair/Primary Examiner, Art Unit 2847
Prosecution Insights