DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Non-Final communication in response to communication filed 1/7/26.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 8, 9, 11, 16 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Carey 9966908.
With respect to claim 1, figure 5 of Carey discloses A circuit comprising: an input network having a first input [In], a second input [In_b], a terminal [Va’], a first output [connection Ra’, Rb’], and a second output [connection Ra, Rb];
a voltage generator [Rff,420,Rff’,424] having an output [Va’] and a control input [Vc], in which the output of the voltage generator is coupled to the terminal; and
a comparator [502] having first [connection Ra’,Rb’] and second [connection Ra, Rb] inputs and an output, in which the first comparator input of the comparator is coupled to the first output of the input network, the second input of the comparator is coupled to the second output of the input network, and the output of the comparator is coupled to the control input.
With respect to claim 8, figure 5 of Carey discloses The circuit of claim 1, further comprising a capacitor coupled between the second input and the output of the comparator. [424]
With respect to claim 9, figure 5 of Carey discloses The circuit of claim 1, further comprising a controller [circuit providing In] having an output coupled to the first input of the input network, in which the controller is configurable to provide a modulated signal [In] at the output of the controller.
With respect to claim 11, figure 5 of Carey discloses a circuit, comprising: an input divider network [404,408,Ra’,412,416,Ra] configurable to provide a first signal [connection Ra’,Rb’] and a second signal [connection Ra, Rb] at its outputs, responsive to a third signal [In] at its input, a ground signal [connected to 434], a first voltage [Va], and a second voltage [Va’];
a voltage generator having a control input [Vc/Vc’] and configurable to provide the first voltage and the second voltage, responsive to a state of the control input; and
a comparator [502] configurable to set a state of the control input responsive to a comparison between the first and second signals.
With respect to claim 16, figure 5 of Carey discloses the circuit of claim 11, wherein the voltage generator is configurable to provide the first voltage at a first output [Va] and the second voltage at a second output [Va’], in which the second voltage changes between a first value and a second value [Fig. 3] responsive to the state of the control input.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Carey 9966908.
With respect to claim 10, figure 5 of Carey discloses the circuit of claim 9, but does not disclose further comprising a first integrated circuit and a second integrated circuit, wherein the first integrated circuit includes the controller, and the second integrated circuit includes at least part of the input divider network and the comparator, and the signal output of the controller is directly coupled to the first divider input of the input network.
However, it would have been obvious to one skilled in the art at the time the invention was made to arrange the parts in integrated circuits as disclosed above since it has been held that rearranging parts of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70.
Allowable Subject Matter
Claims 19 and 20 are allowed.
Claims 2-7, 12-15, 17 and 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RYAN C JAGER whose telephone number is (571)272-7016. The examiner can normally be reached on 8:30 - 5:30 PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lincoln Donovan can be reached on 571-272-7016. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/RYAN JAGER/
Primary Examiner, Art Unit 2842
2/13/26