DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 2/18/2026 have been fully considered but they are not persuasive.
35 USC § 101
Applicant argues that reciting the computer-readable medium as “non-transitory” is patent eligible subject matter and dispositive as held by the PTAB and according to USPTO guidance on subject matter eligibility.
The Examiner notes that while reciting may be normally sufficient to establish subject matter eligibility in computer readable medium claims, it is not the case in the present application. In this instance, Applicant has acted as their own lexicographer (see MPEP 2111.01 IV) to redefine what the ordinary meaning of “non-transitory” would be understood by one of ordinary skill in the art to mean. As per paragraph 105 of the specification, a “non-transitory computer-readable medium” “may be any available medium, or combination of multiple media, that can be accessed by a computer”. Because a signal or carrier wave are examples of mediums “that can be accessed by a computer”, claims 18-24 are directed to non-statutory subject matter.
35 USC § 103
Applicant argues that Iwai is silent as to "reading, at a second time, the data from the one or more memory cells of the memory device based on disabling the first error correction capability," as recited in claim 1 because Iwai discusses discarding data with an uncorrectable error and then issuing a new read command as the next step.
The Examiner asserts that Iwai teaches re-reading data “based on disabling the first error correction capability” because the first error correction capability is bypassed by Iwai upon re-read (Fig. 7, 30 and paragraph 72). It is also noted that one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986). In this instance, Drake teaches disabling a first error correction capability of the memory system (Fig. 2, 82) due to an uncorrectable error type (Fig. 2, 76-78). Since Iwai teaches re-reading when an uncorrectable error is detected and bypassing ECC through data line 30, it would have been obvious for one of ordinary skill in the art before the effective filing date to perform the re-read of Iwai on the memory upon encountering an uncorrectable error and disabling ECC as taught by Drake.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 18-24 are rejected under 35 U.S.C. 101 because the claimed invention is directed to non-statutory subject matter. The claim(s) does/do not fall within at least one of the four categories of patent eligible subject matter because a “non-transitory computer-readable medium” “may be any available medium, or combination of multiple media, that can be accessed by a computer” (specification paragraph 105). Thus, a non-transitory computer-readable medium as claimed may comprise a signal or carrier wave, which are mediums “that can be accessed by a computer”.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-10 and 12-25 is/are rejected under 35 U.S.C. 103 as being unpatentable over Drake et al (US Pat. 5,535,226; hereinafter referred to as Drake) in view of Iwai et al (US Pat. Pub. 2020/0286576; hereinafter referred to as Iwai) in view of Kim et al (US Pat. 10,061,641; hereinafter referred to as Kim).
As per claims 1, 18, 25: Drake teaches a method by a memory system and non-transitory computer-readable medium, comprising:
one or more memory devices (Fig. 1);
reading, at a first time (col. 1, lines 50-53; Fig. 2, 76: a read is necessary to determine whether an error is uncorrectable), data from one or more memory cells of a memory device (col. 4, lines 27-29);
disabling a first error correction capability of the memory system (Fig. 2, 82) based on determining that data read from the one or more memory cells of the memory system comprises one or more errors of a first type (Fig. 2, 76-78; uncorrectable error);
Not explicitly disclosed is reading, at a second time, the data from the one or more memory cells of the memory device based on disabling the first error correction capability. However, Iwai in an analogous art teaches reading, at a second time, a data from a memory device and bypassing ECC upon the re-read (paragraph 72; Fig. 7, 30).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date to re-read the memory upon detecting an uncorrectable error and disabling ECC as taught by Drake. This modification would have been obvious for one of ordinary skill in the art at the time of filing because it is suggested by Drake in col. 6, lines 61-65 (ECC is reenabled to attempt to recover from the uncorrectable error. Therefore data is necessarily re-read for reattempting the ECC).
Also not explicitly disclosed is transmitting the data to a host device based on determining that the data does not comprise the one or more errors of the first type based on reading the data from the one or more memory cells of the memory system for the second time. However, Kim in an analogous art teaches transmitting the data to a host (Fig. 17) based on determining that the error is correctable (Fig. 11, S440 Pass).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date to output correctable data to the host. This modification would have been obvious for one of ordinary skill in the art at the time of filing because the purpose of memory ECC is to output corrected data.
As per claims 2, 19:
Drake teaches the method of claim 1 and non-transitory computer-readable medium of claim 18, where determining that the data read from the one or more memory cells of the memory system comprises the one or more errors of the first type comprises: failing to correct at least one error in the data (Fig. 2, 76). Not explicitly disclosed is failing to correct at least one error in the data using a second error correction capability of the memory system. However, Kim in an analogous art teaches disabling a first error correction capability (col. 6, lines 24-25) and using a second error correction capability of the memory system (Fig. 2, 224).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date to use a first and second error correction capability as taught by Kim. This modification would have been obvious for one of ordinary skill in the art at the time of filing because it could have been used as a stopping criterion for ECC (col. 5, lines 61-63).As per claim 3: Kim further teaches the method of claim 2, wherein the second error correction capability of the memory system comprises a Reed-Solomon error correction code (col. 5, lines 58-59).
As per claims 4, 20: Kim further teaches the method of claim 1 and non-transitory computer-readable medium of claim 18, further comprising:
reading, at a third time, second data from one or more second memory cells of the memory system (Fig. 11, S410);
correcting the one or more errors in the second data using a second error correction capability of the memory system (Fig. 11, S410 ECC decoding) based on determining that the second data comprises one or more errors of a second type (S440 pass for correctable errors); and
transmitting the second data to the host device based on correcting the one or more errors in the second data using the second error correction capability of the memory system (Fig. 11, decoding end; Fig. 17 host).
As per claim 5:
Drake teaches the method of claim 4, wherein: the one or more errors of the first type comprise an uncorrectable error (UE) (Fig. 2, 76 yes); and the one or more errors of the second type comprise a correctable error (CE) (Fig. 2, 76 no).As per claims 6, 21: Kim further teaches the method of claim 1 and non-transitory computer-readable medium of claim 18, further comprising:
reading, at a third time, third data from one or more third memory cells of the memory system (Fig. 11, S410);
determining that the third data comprises zero errors based on reading the third data from the one or more third memory cells of the memory system (Fig. 11, S440 Pass; non-erred data is indicated by a CRC pass); and
transmitting the third data to the host device based on determining that the third data comprises zero errors (Fig. 11, decoding end; Fig. 17 host).
As per claims 7, 22:
Drake teaches the method of claim 1 and non-transitory computer-readable medium of claim 18, further comprising:
determining that the data comprises one or more errors of a second type based on determining that the data does not comprise the one or more errors of the first type (Fig. 2, 76 No); and
correcting the one or more errors of the second type using a second error correction capability of the memory system based on determining that the data comprises the one or more errors of the second type (Fig. 2, 88; Kim Fig. 2, 226), wherein transmitting the data to the host device is based on correcting the one or more errors of the second type (Kim Fig. 2, output of 226).
As per claims 8, 23:
Drake and Kim further teaches the method of claim 1 and non-transitory computer-readable medium of claim 18, wherein determining that the data does not comprise the one or more errors of the first type comprises: determining that the data comprises zero errors, wherein transmitting the data to the host device is based on determining that the data comprises zero errors (non-erred data is indicated by a CRC pass as taught by Kim and output to the host).As per claims 9, 24: Drake further teaches the method of claim 1 and non-transitory computer-readable medium of claim 18, further comprising: reading a first bit value from a mode register of the memory system (Fig. 1, 16), wherein the first bit value indicates that the first error correction capability of the memory system is configured to be disabled (col. 4, lines 46-48), wherein disabling the first error correction capability of the memory system is based on reading the first bit value from the mode register of the memory system (Fig. 2, 80-82).
As per claim 10: Drake further teaches the method of claim 1, further comprising:
receiving, from the host device, a command comprising an indication to write a second bit value to a mode register of the memory system based on determining that the data read from the one or more memory cells of the memory system comprises the one or more errors of the first type (Fig. 2, 78; it would be obvious to have a host command since the host controls the system); and
writing the second bit value to the mode register of the memory system based on receiving the command, wherein disabling the first error correction capability of the memory system is based on writing the second bit value to the mode register (Fig. 2, 80-82).
As per claim 12:
Drake further teaches the method of claim 1, further comprising: rereading the data from the one or more memory cells of the memory system (col. 6, lines 61-65; ECC is reenabled to attempt to recover from the uncorrectable error. Therefore data is necessarily re-read for reattempting the ECC), wherein the command comprises an indication to disable the first error correction capability of the memory system (Fig. 2, 82). Not explicitly disclosed is receiving, from the host device and based on determining that the data comprises the one or more errors of the first type a command to reread the data.
However, Iwai in an analogous art teaches a read command for rereading a data upon determining that the data comprises an uncorrectable error (paragraph 72). Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date to reread the data of Drake in response to an uncorrectable error. This modification would have been obvious for one of ordinary skill in the art at the time of filing because Drake teaches that in response to data of a first type (Fig. 2, 78), ECC can be re-enabled to attempt to recover from the first type error (col. 6, lines 61-65), and a re-read command would have facilitated that.
As per claim 13: Iwai further teaches the method of claim 12, wherein the command comprises a write command, a write auto precharge command, a read command, or a read auto precharge command (paragraph 72; read command).
As per claim 14:
Drake further teaches the method of claim 1, further comprising: enabling the first error correction capability of the memory system based on transmitting the data to the host device (Fig. 1, 11; see also Kim Fig. 2).As per claim 15: Drake further teaches the method of claim 1, wherein the first error correction capability comprises an on-die error correction code (Fig. 1, 11).
As per claim 16: Drake further teaches the method of claim 1, further comprising:
determining that the data read from the one or more memory cells of the memory system at the first time comprises the one or more errors of the first type (Fig. 2, 76 YES); and
determining that the data read from the one or more memory cells of the memory system at the second time does not comprise the one or more errors of the first type (Fig. 2, 76 NO).
As per claim 17:
Drake et al teach the method of claim 1. Not explicitly disclosed is further comprising:
reading, at a third time, second data from one or more second memory cells of the memory device;
rereading, at a fourth time, the second data from the one or more second memory cells of the memory device; and
transmitting an indication to the host device based on determining that the second data comprises one or more errors of the first type based on rereading the second data from the one or more second memory cells of the memory system.
However, Iwai in an analogous art teaches reading data from a memory cell (Fig. 2, S101), rereading the data (paragraph 72), and notifying a host when the data has uncorrectable errors (S106; paragraph 4). Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date to combine the teachings of Iwai with Drake et al in order to notify a host of uncorrectable errors.
Claim(s) 11 is rejected under 35 U.S.C. 103 as being unpatentable over Drake in view of Iwai in view of Kim in view of Van Antwerpen et al (US Pat. Pub. 2019/0122007; hereinafter referred to as Van Antwerpen).
As per claim 11:
Drake et al teach the method of claim 10. Not explicitly disclosed is further comprising: receiving, from the host device, a secret key, wherein writing the second bit value to the mode register of the memory system is based on the secret key. However, Van Antwerpen in an analogous art teaches a memory configured to receive a secret key from a host for encryption (paragraph 32).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date to secret key data in Drake. This modification would have been obvious for one of ordinary skill in the art at the time of filing because it would have offered a level of security (paragraph 36).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STEVE N NGUYEN whose telephone number is (571)272-7214. The examiner can normally be reached M-F 9-5.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Mark Featherstone can be reached at 571-270-3750. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/STEVE N NGUYEN/Primary Examiner, Art Unit 2111