Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claim Rejections - 35 USC § 102
1. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
2. Claim(s) 12-16, is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Edahiro (Pub. No.: US 2007/0104002).
3. Regarding independent claim 12, Edahiro teaches a first sense amplifier (Fig. 15, #13); a first bit line (Fig. 15, LBL0 for example) coupled to the first sense amplifier (Fig. 15, #13); a second sense amplifier (Fig. 15, #50); a second bit line (Fig. 15, GBL0 for example) coupled to the second sense amplifier (Fig. 15, #50); and a bit line switch (Fig. 15, #16-0 for example) coupled to the first bit line (Fig. 15, LBL0 for example) and the second bit line (Fig. 15, GBL0 for example), wherein the bit line switch (Fig. 15, #16-0 for example) is configured to provide (Fig. 15, RCSL0=“H”) a conductive path (Fig. 15, Precharge) between the first bit line (Fig. 15, LBL0 for example) and the second bit line (Fig. 15, GBL0 for example) when activated (Fig. 15, RCSL0=“H”).
4. Regarding claim 13, Edahiro teaches a decoder circuit (Fig. 15, #12) configured to activate (Fig. 15, RCSL0=“H”) the bit line switch (Fig. 14, #16-0).
5. Regarding claim 14, Edahiro teaches the bit line switch (Fig. 14, #16-0) is configured to be activated during a threshold voltage compensation phase (Fig. 15, RCSL0=“H”).
6. Regarding claim 15, Edahiro teaches the bit line switch (Fig. 15, #16-0) is configured to be deactivated during a memory access phase (Fig. 15, paragraph [0083]).
7. Regarding claim 16, Edahiro teaches second sense amplifier is not coupled to a another bit line (Fig. 15, only coupled to GBL0).
Allowable Subject Matter
10. Claims 1-11, 17-20 are allowed.
11. With respect to independent claims 1, there is no teaching, suggestion, or motivation for combination in the prior art to a plurality of bit line switches, each bit line switch of the plurality of bit line switches coupled to a respective bit line of the second plurality of bit lines and to a respective bit line of the third plurality of bit lines, each bit line switch configured to provide a conductive path between the respective bit line of the second plurality of bit lines and the respective bit line of the third plurality of bit lines when activated.
12. With respect to dependent claims 2-6, since these claims are depending on claim 1, therefore claims 2-6 are allowable subject matter.
13. With respect to independent claims 7, there is no teaching, suggestion, or motivation for combination in the prior art to wherein the first bit line and the second bit line having the conductive path therebetween via bit line switch during the threshold voltage compensation operation; and deactivating the bit line switch before activating a word line of the memory mat to access a first memory cell coupled to the first bit line and to access a second memory cell coupled to the second bit line.
14. With respect to dependent claims 8-11, since these claims are depending on claim 7, therefore claims 8-11 are allowable subject matter.
13. With respect to independent claims 17, there is no teaching, suggestion, or motivation for combination in the prior art to wherein the plurality of single-ended sense amplifiers are not coupled to the plurality of second bit lines; and a plurality of bit line switches, each bit line switch of the plurality of bit line switches configured to provide a conductive path between a respective one of the plurality of first bit lines and a respective one of the plurality of second bit lines in response to a switch activation signal.
14. With respect to dependent claims 18-20, since these claims are depending on claim 17, therefore claims 18-20 are allowable subject matter.
Conclusion
15. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure, Kajigaya et al (Pub. No.: US 2009/0251948A1).
Kajigaya et al (Pub. No.: US 2009/0251948A1) shows two bit lines connected by a transistor.
16. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Han Yang whose telephone is (571) 270-3048. The examiner can normally be reached on Monday-Friday 8am-5pm with alternate Friday off. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Richard Elms can be reached on (571) 272-1869. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
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HY
02/25/2026
/HAN YANG/
Primary Examiner, Art Unit 2824
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