DETAILED ACTION
Claims 1-20 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that use a term used as a substitute for “means” that is a generic placeholder, and are thus being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are first recited in Claims 1, 12, and 15:
1. and a central unit coupled with the first temperature controller and the element, the central unit configured to dynamically control…
12. and a first central unit coupled with the first element and the first plurality of temperature controllers, the first central unit configured to dynamically control…
15. and a second central unit coupled with the second element and the second plurality of temperature controllers, the second central unit configured to dynamically control…
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2 are rejected under 35 U.S.C. 103 as being unpatentable over Vaishampayan (US 20150348226 A1) in view of Gaskins (US 20070116085 A1).
Regarding Claim 1, Vaishampayan teaches a system comprising:
a first temperature controller configured to throttle an element of a semiconductor device (
Vaishampayan discloses, “In one embodiment, the operating system 124 adjusts the operation of the GPU 106 to mitigate the thermal profile of the device 100. In this embodiment, the operating system 124 includes a thermal daemon (thermald) 110 and kernel 112,” ¶ 0026, “FIG. 6 is a block diagram of one embodiment of a thermal daemon, thermald, 110 that manages GPU throttling based on the thermal data of the device. In one embodiment, thermald 110 includes a GPU throttling module 600 that determines whether to selectively apply or relax a GPU throttle to a priority. In one embodiment, the GPU throttling module 600 includes a receive thermal data module 602, compare higher thermal threshold module 604, compare lower thermal threshold 606, increase GPU throttling module 608, and decrease GPU throttling module 610… The increase GPU throttling module 608 increases the GPU throttling for one or more processes as described in FIG. 3, block 308 above. The decrease GPU throttling module 610 decreases the GPU throttling for one or more processes as described in FIG. 3, block 310 above,” ¶ 0036, and “Portions of what was described above may be implemented with logic circuitry such as a dedicated logic circuit or with a microcontroller or other form of processing core that executes program code instructions. Thus processes taught by the discussion above may be performed with program code such as machine-executable instructions that cause a machine that executes these instructions to perform certain functions. In this context, a ‘machine’ may be … electronic circuitry disposed on a semiconductor chip (e.g., “logic circuitry” implemented with transistors) designed to execute instructions such as a general-purpose processor and/or a special-purpose processor,” ¶ 0046.
The claimed “first temperature controller” is mapped to the disclosed “thermald”, which throttles GPUs of the device.
The claimed “semiconductor device” is mapped to the disclosed “device 100”, which contains the GPUs that are throttled by the thermald.
The claimed “element” is mapped to the disclosed “GPU”.);
a first throttling table, the first temperature controller configured to sequentially apply throttling steps to the element based on the first throttling table (
Vaishampayan discloses, “In one embodiment, the device can be configured for several different thermal thresholds, with each thermal threshold having different GPU throttling levels. In this embodiment, crossing a thermal threshold can mean that thermald 110 adjusts a set of GPU utilization values for different priority level processes,” ¶ 0026, “In one embodiment, process 300 is performed by a thermal daemon to manage I/O throttling, such as thermald 112 as described above in FIG. 1… If the thermal data is greater than a higher threshold, process 300 adjusts the GPU throttling table to increase the GPU throttling at block 308. In one embodiment, process 300 adjusts the GPU throttling table by throttling one or more of the different GPU utilizations for one, some, or all of the process priorities,” ¶ 0031, and “In one embodiment, thermald 110 includes a GPU throttling module 600 that determines whether to selectively apply or relax a GPU throttle to a priority. In one embodiment, the GPU throttling module 600 includes a receive thermal data module 602, compare higher thermal threshold module 604, compare lower thermal threshold 606, increase GPU throttling module 608, and decrease GPU throttling module 610… The increase GPU throttling module 608 increases the GPU throttling for one or more processes as described in FIG. 3, block 308 above. The decrease GPU throttling module 610 decreases the GPU throttling for one or more processes as described in FIG. 3, block 310 above,” ¶ 0036.
The claimed “first throttling table” is mapped to the disclosed “GPU throttling table”.
The claimed “throttling steps” is mapped to the disclosed “GPU throttling level” that is modified each time a thermal threshold is crossed. This means that the throttling steps are applied sequentially based on the thermal thresholds being crossed over time, either by the decrease GPU throttling module 610 or the increase GPU throttling module 608, both of which are part of the thermald.);
the first temperature controller configured to dynamically control (
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Vaishampayan discloses, “In one embodiment, the operating system 124 adjusts the operation of the GPU 106 to mitigate the thermal profile of the device 100. In this embodiment, the operating system 124 includes a thermal daemon (thermald) 110 and kernel 112. In this embodiment, thermald 110 is daemon that selectively throttles the GPU operations of one or more running processes in order to mitigate the thermal environment of the device 100,” ¶ 0026,
“In one embodiment, process 300 is performed by a thermal daemon to manage I/O throttling, such as thermald 112 as described above in FIG. 1… If the thermal data is greater than a higher threshold, process 300 adjusts the GPU throttling table to increase the GPU throttling at block 308,” ¶ 0031.
and “FIG. 6 is a block diagram of one embodiment of a thermal daemon, thermald, 110 that manages GPU throttling based on the thermal data of the device. In one embodiment, thermald 110 includes a GPU throttling module 600 that determines whether to selectively apply or relax a GPU throttle to a priority. In one embodiment, the GPU throttling module 600 includes a receive thermal data module 602, compare higher thermal threshold module 604, compare lower thermal threshold 606, increase GPU throttling module 608, and decrease GPU throttling module 610. In one embodiment, the receive thermal data module 602 receives the thermal data as described in FIG. 3, block 302 above,” ¶ 0036.).
Vaishampayan does not teach a central unit coupled with the first temperature controller and the element, the central unit configured to dynamically control, via the first controller, the throttling steps applied to the element for thermal control of the semiconductor device.
However, Gaskins teaches a central unit coupled with the first temperature controller and the element, the central unit configured to dynamically control, via the first controller, the throttling steps applied to the element for thermal control of the semiconductor device (
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Gaskins discloses, “An integrated circuit (IC) according to an embodiment of the present invention includes a temperature sensor, configurable temperature profile logic, at least one controller, and temperature control logic,” ¶ 0009, and “In this case, the temperature control logic controls each controller to maintain the operating temperature value within either the maximum or the configured operating temperature range,” ¶ 0011.
The claimed “central unit” is mapped to the disclosed “temperature control logic”, which controls several controllers to maintain a temperature for an integrated circuit.
As can be seen in Gaskins’ figure, the temperature control logic is coupled to several temperature controllers 117, 119, 121, 123, and 125, and controls each of the controllers in order to maintain an operating temperature value.
This is consistent with the present application’s specification, which states that “In aspects, a central unit may be coupled with an element of the semiconductor device and one or more temperature controllers configured to sequentially apply throttling steps to the element to thermally control the element…,” ¶ 0023.
After the combination of Vaishampayan with Gaskins, Vaishampayan uses the temperature control logic from Gaskins, in order to control its own thermald for maintaining temperature of the GPU.).
Vaishampayan and Gaskins are both considered to be analogous to the claimed invention because they are in the same field of computer thermal management. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Vaishampayan to incorporate the teachings of Gaskins and provide a central unit coupled with the first temperature controller and the element, the central unit configured to dynamically control, via the first controller, the throttling steps applied to the element for thermal control of the semiconductor device. Doing so would help provide capabilities for adding more controllers for controlling the temperature more efficiently, with the central unit managing each controller, and allow the flexibility to find the optimal temperature control for a specific situation (Gaskins discloses, “The temperature control logic controls one or more controllers to maintain the operating temperature value within the configured operating temperature range,” ¶ 0009.).
Regarding Claim 2, Vaishampayan in view of Gaskins teaches the system of claim 1, wherein the central unit commands the first temperature controller to apply a throttling step based on a performance state of the element (
Vaishampayan discloses, “In one embodiment, under conditions of a low thermal load of the device 100, each of the priorities will have a high GPU utilization (e.g. near or at 100%). As the thermal load on the device 100 increases, thermald 110 adjusts the priority GPU utilization of one or more of the different process priorities,” ¶ 0026, and “In one embodiment, thermald 110 includes a GPU throttling module 600 that determines whether to selectively apply or relax a GPU throttle to a priority. In one embodiment, the GPU throttling module 600 includes a receive thermal data module 602, compare higher thermal threshold module 604, compare lower thermal threshold 606, increase GPU throttling module 608, and decrease GPU throttling module 610,” ¶ 0036.
Here, the thermald applies the throttling step (adjusting priority GPU utilization) to the element (GPU) based on the thermal load of the device from the current GPU utilization.
After the combination of Vaishampayan with Gaskins, the temperature control logic of Gaskins would command the thermald from Vaishampayan to apply this throttling step.).
Vaishampayan and Gaskins are both considered to be analogous to the claimed invention because they are in the same field of computer thermal management. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Vaishampayan to incorporate the teachings of Gaskins and provide wherein the central unit commands the first temperature controller to apply a throttling step based on a performance state of the element. Doing so would help provide capabilities for adding more controllers for controlling the temperature more efficiently, with the central unit commanding each controller to apply their own throttling steps. (Gaskins discloses, “The temperature control logic controls one or more controllers to maintain the operating temperature value within the configured operating temperature range,” ¶ 0009.).
Claims 3-4 are rejected under 35 U.S.C. 103 as being unpatentable over Vaishampayan (US 20150348226 A1) in view of Gaskins (US 20070116085 A1) and Hermerding (US 20060064999 A1).
Regarding Claim 3, Vaishampayan in view of Gaskins teaches the system of claim 1, further comprising: a second temperature controller configured to throttle the element; (
Gaskins discloses, “An integrated circuit (IC) according to an embodiment of the present invention includes a temperature sensor, configurable temperature profile logic, at least one controller, and temperature control logic,” ¶ 0009, “In this case, the temperature control logic controls each controller to maintain the operating temperature value within either the maximum or the configured operating temperature range,” ¶ 0011.
Here, multiple controllers maintain the operating temperature value of an integrated circuit. After the combination of Vaishampayan with Gaskins, the temperature control logic of Gaskins is now explicitly configured to dynamically control the throttling steps applied, for each controller, to the GPU as specified by Vaishampayan.)
Vaishampayan and Gaskins are both considered to be analogous to the claimed invention because they are in the same field of computer thermal management. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Vaishampayan to incorporate the teachings of Gaskins and provide further comprising: a second temperature controller configured to throttle the element; the second temperature controller configured to sequentially apply throttling steps to the element, wherein the central unit is coupled with the second temperature controller and is configured to dynamically control the throttling steps applied, by the second controller, to the element for thermal control of the semiconductor device. Doing so would help provide utilizing multiple controllers for controlling the temperature more efficiently, with the central unit commanding each controller to apply their own throttling steps. (Gaskins discloses, “The temperature control logic controls one or more controllers to maintain the operating temperature value within the configured operating temperature range,” ¶ 0009.).
Vaishampayan in view of Gaskins does not teach a second throttling table, the second temperature controller configured to sequentially apply throttling steps to the element based on the second throttling table.
However, Hermerding teaches a second throttling table, the second temperature controller configured to sequentially apply throttling steps to the element based on the second throttling table (
Hermerding discloses, “FIGS. 5-8 illustrate one embodiment of an implementation for a software reporting structure that may be used by a thermal management policy to determine which devices to thermally manage in a system. The software reporting structure may include one or more device power tables, one or more device throttle state tables, a device throttle control object, and one or more thermal influence tables,” ¶ 0044.
Here, multiple throttling tables (device throttle state tables) can be used.
After the combination of Vaishampayan in view of Gaskins, with Hermerding, each of the controllers from Vaishampayan in view of Gaskins would apply throttling steps based on its own assigned throttling table as specified by Hermerding.).
Vaishampayan in view of Gaskins, and Hermerding are both considered to be analogous to the claimed invention because they are in the same field of computer thermal management. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Vaishampayan in view of Gaskins to incorporate the teachings of Hermerding and provide a second throttling table, the second temperature controller configured to sequentially apply throttling steps to the element based on the second throttling table. Doing so would help allow for utilizing the multiple throttling tables to perform more advanced throttling in order to more efficiently manage the temperature of the element.
Regarding Claim 4, Vaishampayan in view of Gaskins and Hermerding teaches the system of claim 3, wherein the central unit has access to the first throttling table (
Vaishampayan discloses, “In one embodiment, process 300 is performed by a thermal daemon to manage I/O throttling, such as thermald 112 as described above in FIG. 1… If the thermal data is greater than a higher threshold, process 300 adjusts the GPU throttling table to increase the GPU throttling at block 308. In one embodiment, process 300 adjusts the GPU throttling table by throttling one or more of the different GPU utilizations for one, some, or all of the process priorities,” ¶ 0031.
Here, the thermald (claimed “first temperature controller”) has access to the first throttling table via process 300. After the combination of Vaishampayan with Gaskins, the temperature control logic from Gaskins now has access to the first throttling table via the thermald.)
and to the second throttling table (
Hermerding discloses, “FIGS. 5-8 illustrate one embodiment of an implementation for a software reporting structure that may be used by a thermal management policy to determine which devices to thermally manage in a system. The software reporting structure may include one or more device power tables, one or more device throttle state tables, a device throttle control object, and one or more thermal influence tables,” ¶ 0044.
Here, multiple throttling tables (device throttle state tables) can be used.
After the combination of Vaishampayan in view of Gaskins, with Hermerding, each of the controllers from Vaishampayan in view of Gaskins would apply throttling steps based on its own assigned throttling table as specified by Hermerding. Furthermore, the temperature control logic from Gaskins would be able to access each throttling table through the controller the table is assigned to.).
Vaishampayan and Gaskins are both considered to be analogous to the claimed invention because they are in the same field of computer thermal management. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Vaishampayan to incorporate the teachings of Gaskins and provide wherein the central unit has access to the first throttling table. Doing so would help allow for greater control over the throttling table from a more easily accessible interface of the central unit.
Vaishampayan in view of Gaskins, and Hermerding are both considered to be analogous to the claimed invention because they are in the same field of computer thermal management. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Vaishampayan in view of Gaskins to incorporate the teachings of Hermerding and provide wherein the central unit has access to the second throttling table. Doing so would help allow for greater control over each of the throttling tables from a more easily accessible interface of the central unit.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Vaishampayan (US 20150348226 A1) in view of Gaskins (US 20070116085 A1), Hermerding (US 20060064999 A1), and Stevens (US 20220147128 A1).
Regarding Claim 5, Vaishampayan in view of Gaskins and Hermerding teaches the system of claim 4, wherein the first temperature controller is configured to control a temperature of the element from exceeding a first threshold temperature (
Vaishampayan discloses, “For example and in one embodiment, the thermal threshold can be related to the temperature of the device, a module of the device, fan speed, or some other thermal characteristic. As another example and embodiment, a set of higher thermal threshold could be if the device temperature exceeded 40° C., 45° C., 50° C., etc. In one embodiment, the thermal data may exceed more than one threshold. In another embodiment, the thermal threshold can be based on time of day or user activity. For example and in one embodiment, if process 300 knows that a user is very likely to use the machine in near future (say back from lunch), process 300 may choose to throttle low QoS tasks to leave “thermal headroom” for the task users is likely to perform. This is especially important for devices that do not have fans to actively dissipate heat. If the thermal data is greater than a higher threshold, process 300 adjusts the GPU throttling table to increase the GPU throttling at block 308,” ¶ 0031.).
Vaishampayan in view of Gaskins and Hermerding does not teach wherein the second temperature controller is configured to control an average temperature of the element from exceeding a second threshold temperature.
However, Stevens teaches wherein the second temperature controller is configured to control an average temperature of the element from exceeding a second threshold temperature (
Stevens discloses, “if the average temperature of a CPU over a 24 hour period is greater than a threshold amount, the controller (106) may increase the fan speed so as to bring the average temperature back under the threshold value, even if a user is in front of the computing device,” ¶ 0037.
Here, if an average temperature of a CPU is greater than a threshold temperature, then actions are taken to bring the average temperature back under the threshold temperature.
After the combination of Vaishampayan in view of Gaskins and Hermerding, with Stevens, the second temperature controller from Vaishampayan in view of Gaskins and Hermerding would be configured to control the average temperature of the GPU to ensure it does not exceed a threshold temperature, as specified by Stevens.).
Vaishampayan in view of Gaskins and Hermerding, and Stevens are both considered to be analogous to the claimed invention because they are in the same field of computer thermal management. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Vaishampayan in view of Gaskins and Hermerding to incorporate the teachings of Stevens and provide wherein the second temperature controller is configured to control an average temperature of the element from exceeding a second threshold temperature. Doing so would help ensure that the element does not experience failure due to a high temperature (Stevens discloses, “Such systems and methods 1) enhance system reliability by reducing failure rates relating to high component temperatures,” ¶ 0025.).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Vaishampayan (US 20150348226 A1) in view of Gaskins (US 20070116085 A1), Hermerding (US 20060064999 A1), and DeMoss (US 20230089174 A1).
Regarding Claim 6, Vaishampayan in view of Gaskins and Hermerding teaches the system of claim 4. Vaishampayan in view of Gaskins and Hermerding does not teach wherein the first temperature controller communicates, to the central unit, an application of throttling steps applied to the element.
However, DeMoss teaches wherein the first temperature controller communicates, to the central unit, an application of throttling steps applied to the element (
DeMoss discloses, “In some examples, the HDD performance management computing module 210 can perform the mitigation service at the information handling system 202 including providing a notification to a graphical user interface (GUI) 250 of the display device 214 indicating implementation of the mitigation service. For example, the notification can indicate the speed of the fan 216 is being reduced to, that the CPU 218 is being throttled, or both,” ¶ 0041.
Here, DeMoss’ HDD performance management computing module communicates a notification to a graphical user interface, indicating the degree to which a CPU is being throttled.
After the combination of Vaishampayan in view of Gaskins and Hermerding, with DeMoss, a notification would be sent from Vaishampayan’s claimed first temperature controller to Gaskin’s claimed central unit, and said notification would contain the degree to which Vaishampayan’s GPU is throttled, as specified by DeMoss.).
Vaishampayan in view of Gaskins and Hermerding, and DeMoss are both considered to be analogous to the claimed invention because they are in the same field of computer thermal management. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Vaishampayan in view of Gaskins and Hermerding to incorporate the teachings of DeMoss and provide wherein the first temperature controller communicates, to the central unit, an application of throttling steps applied to the element. Doing so would help allow for the central unit to take further actions based on the notification, in order to improve performance (DeMoss discloses, “The notification can further indicate that further action can be taken in response to user input, such as the mitigation services, to mitigate the performance issues of the HDD 212,” ¶ 0041.).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Vaishampayan (US 20150348226 A1) in view of Gaskins (US 20070116085 A1), Hermerding (US 20060064999 A1), DeMoss (US 20230089174 A1), and Carbone (US 20150277454 A1).
Regarding Claim 7, Vaishampayan in view of Gaskins, Hermerding, and DeMoss teaches the system of claim 6. Vaishampayan in view of Gaskins, Hermerding, and DeMoss does not teach wherein the central unit controls, via the second temperature controller, throttling steps applied to the element based on the application of throttling steps communicated by the first temperature controller.
However, Carbone teaches wherein the central unit controls, via the second temperature controller, throttling steps applied to the element based on the application of throttling steps communicated by the first temperature controller (
Carbone discloses, “In some examples the throttle ratio parameter provides a ratio between the rate at which the first control loop 210 throttles an operating parameter of the first heat source and the rate at which the second control loop 212 throttles an operating parameter of the second heat source 260,” ¶ 0031, and “If the throttle ratio parameter specifies a M:N throttling relationship then the control loop manager 230 keeps track of the number of throttle steps implemented by each control loop and the number of throttle steps necessary to maintain the ratio. For example, if the throttle ratio specifies a 3:1 ratio between the first control loop 210 and the second control loop 212 then the control loop manager tracks the number of throttle steps implemented by the first control loop, and for every three steps implemented by the first control loop 210 the second control loop implements one throttle step.,” ¶ 0043.
Here, the throttling steps applied by a second control loop is based on the throttling steps of a first control loop. After the combination of Vaishampayan in view of Gaskins, Hermerding, and DeMoss, with Carbone, these control loops would be replaced by the controllers of Vaishampayan in view of Gaskins, Hermerding, and DeMoss.).
Vaishampayan in view of Gaskins, Hermerding, and DeMoss, and Carbone are both considered to be analogous to the claimed invention because they are in the same field of computer thermal management. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Vaishampayan in view of Gaskins, Hermerding, and DeMoss to incorporate the teachings of Carbone and provide wherein the central unit controls, via the second temperature controller, throttling steps applied to the element based on the application of throttling steps communicated by the first temperature controller. Doing so would help allow greater control of the temperature of the element by coordinating between the controllers (Carbone discloses, “Accordingly techniques for coordinating control loops for temperature control may find utility, e.g., in electronic devices,” ¶ 0003.).
Claims 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over Vaishampayan (US 20150348226 A1) in view of Gaskins (US 20070116085 A1), Hermerding (US 20060064999 A1), and Huang (US 20070220288 A1).
Regarding Claim 8, Vaishampayan in view of Gaskins and Hermerding teaches the system of claim 4. Vaishampayan in view of Gaskins and Hermerding does not teach wherein the element communicates a current performance status to the central unit.
However, Huang teaches wherein the element communicates a current performance status to the central unit (
Huang discloses, “With reference to FIG. 1, a thermal throttling duty estimation method for a central processing unit (CPU) is provided. The thermal throttling duty estimation method in FIG. 1 for a CPU is implemented in a computer system 30 for adjusting the temperature of the CPU of computer system 30. First, step S200 is executed, wherein the computer system 30 stores a plurality of settings comprising an initial throttle duty (INID), a shutoff threshold temperature (SHFT), an initial throttle threshold temperature (INIT), and a temperature scale (TS) and begins a boot process. The settings may be configured through a basic input/output system (BIOS) and determined through experience,” ¶ 0019, “Next, in step S202, CPU temperature data (CPUT) is received from the CPU. The CPU may periodically deliver current CPU temperature data (CPUT),” ¶ 0020, and “A thermal throttling duty estimation system for a central processing unit (CPU), implemented in a computer system, comprising: a controller coupled to the CPU, receiving CPU temperature data (CPUT) from the CPU; and a thermal management unit coupled to the controller and the CPU, calculating a thermal throttle duty (TTD) based on the CPU temperature data and transmitting the thermal throttle duty to the CPU, wherein the CPU adjusts the CPU performance thereof according to the thermal throttle duty,” Claim 11.
Here, a controller receives a current performance status in the form of temperature data from a CPU. A central unit in the form of a disclosed “thermal management unit” then retrieves the temperature data from the controller for calculations.
After the combination of Vaishampayan in view of Gaskins and Hermerding, with Huang, the GPU from Vaishampayan, similar to a CPU would send its current performance status to the central unit from Gaskins, as specified by Huang.).
Vaishampayan in view of Gaskins and Hermerding, and Huang are both considered to be analogous to the claimed invention because they are in the same field of computer resource management. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Vaishampayan in view of Gaskins and Hermerding to incorporate the teachings of Huang and provide wherein the element communicates a current performance status to the central unit. Doing so would help allow for the central unit to make more informed temperature control decisions based on the performance status.
Regarding Claim 9, Vaishampayan in view of Gaskins, Hermerding, and Huang teaches the system of claim 8, wherein, based on the communicated current performance status, the central unit controls an application of throttling steps applied to the element by the first temperature controller and the second temperature controller (
Huang discloses, “Before calculating the thermal throttle duty (TTD), thermal management unit 36 further determines if the CPU temperature data (CPUT) is greater than the shutoff threshold temperature (SHFT) and, when the CPU temperature data (CPUT) is greater than the shutoff threshold temperature (SHFT), shuts off computer system 30,” ¶ 0020.
Here, Huang discloses that in response to the received CPU temperature data exceeding a threshold temperature, the thermal management unit shuts down the computer system to ensure its safety and integrity.
Vaishampayan in view of Gaskins and Hermerding already teaches that the central unit controls an application of throttling steps applied to the element by the first temperature controller and the second temperature controller (see rejection of Claims 1 and 3). After the combination of Vaishampayan in view of Gaskins and Hermerding, with Huang, this controlling would be based on a communicated current performance status as specified by Huang, replacing the shutdown of the system to ensure the same effect of safety and integrity.).
Vaishampayan in view of Gaskins and Hermerding, and Huang are both considered to be analogous to the claimed invention because they are in the same field of computer thermal management. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Vaishampayan in view of Gaskins and Hermerding to incorporate the teachings of Huang and provide wherein, based on the communicated current performance status, the central unit controls an application of throttling steps applied to the element by the first temperature controller and the second temperature controller. Doing so would help allow for the central unit to make more informed temperature control decisions based on the performance status.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Vaishampayan (US 20150348226 A1) in view of Gaskins (US 20070116085 A1), Hermerding (US 20060064999 A1), and Jambur Sathyanarayana (US 20200310872 A1).
Regarding Claim 10, Vaishampayan in view of Gaskins and Hermerding teaches the system of claim 4. Vaishampayan in view of Gaskins and Hermerding does not teach wherein the first and second temperature controllers request throttling commands from the central unit prior to an application of the throttling steps to the element.
However, Jambur Sathyanarayana teaches wherein the first and second temperature controllers request throttling commands from the central unit prior to an application of the throttling steps to the element (
Jambur Sathyanarayana discloses, “One power management logic unit included in PCU 138 may be a license grant circuit. Such license grant circuit may receive incoming requests for power licenses and based at least in part on one or more budgets, provide license grants to given cores 120 for execution at a given power level,” ¶ 0038.
“The processor 1700 also includes a power management unit (PMU) 1730 that can include summation circuit 1732 and decision circuit 1734,” ¶ 0123,
“The counter logic 1708.sub.0 can provide the sum of power weights to the IccP controller 1710.sub.0, which can determine, based on the sum of power weights, an IccP license request 1736.sub.0 that is associated with a requested maximum current (Icc) of the core and can send the IccP license request 1736.sub.0 to the PMU 1730… Regardless, in response to received license requests for a power license level that exceeds a current power license level, the IccP controller 1710 may be configured to issue a throttle signal to throttle execution of instructions within the core 1702,” ¶ 0126,
“The PMU 1730 may receive IccP a respective license request from each of the cores 1702.sub.0, . . . , 1702.sub.n (and optionally from one or more computation elements such as computation element 1712) and the PMU 1730 may determine a respective license for each of the cores and/or computation elements through a combination of the summation logic 1732 and the decision logic 1734… the IccP controller can indicate to, e.g. a front end of one or more of the cores, that throughput is to be throttled (e.g., execution rate of instructions is to be reduced) and the respective IccP controller of the throttled core can also issue a request for an updated license having a higher Icc. In an embodiment, the throttling and the request for the license can happen before the first instruction in the queue is executed,” ¶ 0127.
The claimed “command” is mapped to the command to execute at a given power level. The disclosed license is the permission to execute the command.
Here, a controller (disclosed “IccP controller”) sends a request, for an updated license for throttling, to a central unit (disclosed “power management unit (PMU)”. Jambur Sathyanarayana’s controller is responsible for throttling a core in a similar manner to how Vaishampayan’s thermald throttles a GPU.
This is consistent with paragraph 29 of the present application’s specification, which states “Prior to applying a throttling step as set forth in the corresponding throttling table 106, the temperature controller 104 may request permission and/or instructions from the central unit 108.”
After the combination of Vaishampayan in view of Gaskins and Hermerding, with Jambur Sathyanarayana, the controllers from Vaishampayan in view of Gaskins and Hermerding, now send requests for throttling commands to the central unit as specified by Jambur Sathyanarayana, prior to the application of the throttling steps to the element.).
Vaishampayan in view of Gaskins and Hermerding, and Jambur Sathyanarayana are both considered to be analogous to the claimed invention because they are in the same field of computer thermal management. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Vaishampayan in view of Gaskins and Hermerding to incorporate the teachings of Jambur Sathyanarayana and provide wherein the first and second temperature controllers request throttling commands from the central unit prior to an application of the throttling steps to the element. Doing so would help ensure greater security by only granting requests for throttling when the conditions necessitate it, in order to prevent malicious access from slowing down the element by excessive throttling.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Vaishampayan (US 20150348226 A1) in view of Gaskins (US 20070116085 A1), Hermerding (US 20060064999 A1), and Winick (US 8327168 B2).
Regarding Claim 11, Vaishampayan in view of Gaskins and Hermerding teaches the system of claim 4. Vaishampayan in view of Gaskins and Hermerding does not teach.
However, Winick teaches wherein a current throttling status is stored in memory in the first temperature controller and stored in memory in the second temperature controller (
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Winick discloses, “A throttle control logic block 303 associated with the memory controller 302 includes a plurality of storage elements for storing a set of appropriate throttle values (TVs) thereat,” Col 4, Lines 22-25, and “Where two TVs are provided, e.g., TV-1 and TV-2 associated with the memory controller 302, the throttle control signal 307 may be placed in one of two states that can select between the two TV settings,” Col 4, Lines 39-43.
Here, a current throttling status in the form of a selected throttle value is stored in the memory of a controller.
After the combination of Vaishampayan in view of Gaskins and Hermerding, with Winick, the current throttling status would be stored in each of the controllers from Vaishampayan in view of Gaskins and Hermerding, as specified by Winick.).
Vaishampayan in view of Gaskins and Hermerding, and Winick are both considered to be analogous to the claimed invention because they are in the same field of computer thermal management. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Vaishampayan in view of Gaskins and Hermerding to incorporate the teachings of Winick and provide wherein a current throttling status is stored in memory in the first temperature controller and stored in memory in the second temperature controller. Doing so would help allow for controlling the temperature more efficiently based on the throttling status (Winick discloses, “which indicates to the throttle control logic of the memory controllers that a lower throttle value ("TV"), as described below, is to be selected, whereby a reduced rate of memory operation cycles are issued to the memory bank 110. Accordingly, the memory bank 110 uses less power when throttled with fewer cycles,” Col 3, Lines 18-23.)
Claims 12-13 are rejected under 35 U.S.C. 103 as being unpatentable over Gaskins (US 20070116085 A1) in view of Vaishampayan (US 20150348226 A1).
Regarding Claim 12, Gaskins teaches a system comprising:
a first plurality of temperature controllers individually configured to control a temperature of a first element within a semiconductor device (
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Gaskins discloses, “An integrated circuit (IC) according to an embodiment of the present invention includes a temperature sensor, configurable temperature profile logic, at least one controller, and temperature control logic,” ¶ 0009, and “In this case, the temperature control logic controls each controller to maintain the operating temperature value within either the maximum or the configured operating temperature range,” ¶ 0011.
As can be seen in Gaskins’ figure, the temperature control logic is coupled to several temperature controllers 117, 119, 121, 123, and 125, and controls each of the controllers in order to maintain an operating temperature value.);
and a first central unit coupled with the first element and the first plurality of temperature controllers (
Gaskins discloses, “An integrated circuit (IC) according to an embodiment of the present invention includes a temperature sensor, configurable temperature profile logic, at least one controller, and temperature control logic,” ¶ 0009, and “In this case, the temperature control logic controls each controller to maintain the operating temperature value within either the maximum or the configured operating temperature range,” ¶ 0011.
The claimed “central unit” is mapped to the disclosed “temperature control logic”, which controls several controllers to maintain a temperature for an integrated circuit.
As can be seen in Gaskins’ figure, the temperature control logic is coupled to several temperature controllers 117, 119, 121, 123, and 125, and controls each of the controllers in order to maintain an operating temperature value.
This is consistent with the present application’s specification, which states that “In aspects, a central unit may be coupled with an element of the semiconductor device and one or more temperature controllers configured to sequentially apply throttling steps to the element to thermally control the element…,” ¶ 0023.),
.
Gaskins does not teach a first plurality of throttling tables, each throttling table of the first plurality of throttling tables corresponding to an individual temperature controller of the first plurality of temperature controllers; or the first central unit configured to dynamically control throttling steps applied to the first element by the individual temperature controllers of the first plurality of temperature controllers for thermal control of the semiconductor device.
However, Vaishampayan teaches a first plurality of throttling tables, each throttling table of the first plurality of throttling tables corresponding to an individual temperature controller of the first plurality of temperature controllers (
Vaishampayan discloses, “In one embodiment, the device can be configured for several different thermal thresholds, with each thermal threshold having different GPU throttling levels. In this embodiment, crossing a thermal threshold can mean that thermald 110 adjusts a set of GPU utilization values for different priority level processes,” ¶ 0026, “In one embodiment, process 300 is performed by a thermal daemon to manage I/O throttling, such as thermald 112 as described above in FIG. 1… If the thermal data is greater than a higher threshold, process 300 adjusts the GPU throttling table to increase the GPU throttling at block 308. In one embodiment, process 300 adjusts the GPU throttling table by throttling one or more of the different GPU utilizations for one, some, or all of the process priorities,” ¶ 0031, and “In one embodiment, thermald 110 includes a GPU throttling module 600 that determines whether to selectively apply or relax a GPU throttle to a priority. In one embodiment, the GPU throttling module 600 includes a receive thermal data module 602, compare higher thermal threshold module 604, compare lower thermal threshold 606, increase GPU throttling module 608, and decrease GPU throttling module 610… The increase GPU throttling module 608 increases the GPU throttling for one or more processes as described in FIG. 3, block 308 above. The decrease GPU throttling module 610 decreases the GPU throttling for one or more processes as described in FIG. 3, block 310 above,” ¶ 0036.
The claimed “throttling table” is mapped to the disclosed “GPU throttling table”.
After the combination of Gaskins with Vaishampayan, each of the first plurality of temperature controllers from Gaskins would have a throttling table assigned to it, as specified by Vaishampayan.);
and the first central unit configured to dynamically control throttling steps applied to the first element by the individual temperature controllers of the first plurality of temperature controllers for thermal control of the semiconductor device (
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Vaishampayan discloses, “In one embodiment, the operating system 124 adjusts the operation of the GPU 106 to mitigate the thermal profile of the device 100. In this embodiment, the operating system 124 includes a thermal daemon (thermald) 110 and kernel 112. In this embodiment, thermald 110 is daemon that selectively throttles the GPU operations of one or more running processes in order to mitigate the thermal environment of the device 100,” ¶ 0026, and “FIG. 6 is a block diagram of one embodiment of a thermal daemon, thermald, 110 that manages GPU throttling based on the thermal data of the device. In one embodiment, thermald 110 includes a GPU throttling module 600 that determines whether to selectively apply or relax a GPU throttle to a priority,” ¶ 0036.
The claimed “throttling steps” is mapped to the disclosed “GPU throttling level” that is modified each time a thermal threshold is crossed. This means that the throttling steps are applied sequentially based on the thermal thresholds being crossed over time, either by the decrease GPU throttling module 610 or the increase GPU throttling module 608, both of which are part of thermald.
After the combination of Gaskins with Vaishampayan, the temperature control logic from Gaskins would dynamically control throttling steps applied to the first element by the individual temperature controllers of the first plurality of temperature controllers for thermal control of the semiconductor device.).
Gaskins and Vaishampayan are both considered to be analogous to the claimed invention because they are in the same field of computer thermal management. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Gaskins to incorporate the teachings of Vaishampayan and provide a first plurality of throttling tables, each throttling table of the first plurality of throttling tables corresponding to an individual temperature controller of the first plurality of temperature controllers; and the first central unit configured to dynamically control throttling steps applied to the first element by the individual temperature controllers of the first plurality of temperature controllers for thermal control of the semiconductor device. Doing so would help provide greater control of the temperature of the element via the throttling table. (Vaishampayan discloses, “If the thermal data is greater than a higher threshold, process 300 adjusts the GPU throttling table to increase the GPU throttling at block 308. In one embodiment, process 300 adjusts the GPU throttling table by throttling one or more of the different GPU utilizations for one, some, or all of the process priorities,” ¶ 0031.).
Regarding Claim 13, Gaskins in view of Vaishampayan teaches the system of claim 12, wherein the first central unit dynamically controls the throttling steps applied by the individual temperature controllers of the first plurality of temperature controllers based on a current performance state of the first element (
Vaishampayan discloses, “If the thermal data is greater than a higher threshold, process 300 adjusts the GPU throttling table to increase the GPU throttling at block 308. In one embodiment, process 300 adjusts the GPU throttling table by throttling one or more of the different GPU utilizations for one, some, or all of the process priorities,” ¶ 0031, “In one embodiment, the receive thermal data module 602 receives the thermal data as described in FIG. 3, block 302 above. The compare higher thermal threshold module 604 compares the thermal data with a higher thermal threshold as described in FIG. 3, block 304 above. The compare lower thermal threshold 606 compares the thermal data with a lower thermal threshold as described in FIG. 3, block 306 above. The increase GPU throttling module 608 increases the GPU throttling for one or more processes as described in FIG. 3, block 308 above. The decrease GPU throttling module 610 decreases the GPU throttling for one or more processes as described in FIG. 3, block 310 above,” ¶ 0036.
After the combination of Gaskins with Vaishampayan, the temperature control logic from Gaskins dynamically controls the throttling steps applied by its controllers based on thermal data as specified by Vaishampayan.).
Gaskins and Vaishampayan are both considered to be analogous to the claimed invention because they are in the same field of computer thermal management. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Gaskins to incorporate the teachings of Vaishampayan and provide wherein the first central unit dynamically controls the throttling steps applied by the individual temperature controllers of the first plurality of temperature controllers based on a current performance state of the first element. Doing so would help provide greater control of the temperature of the element based on its performance state. (Vaishampayan discloses, “If the thermal data is greater than a higher threshold, process 300 adjusts the GPU throttling table to increase the GPU throttling at block 308. In one embodiment, process 300 adjusts the GPU throttling table by throttling one or more of the different GPU utilizations for one, some, or all of the process priorities,” ¶ 0031.).
Claims 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over Gaskins (US 20070116085 A1) in view of Vaishampayan (US 20150348226 A1), Louie (US 20250068227 A1), and Hermerding (US 20060064999 A1).
Regarding Claim 15, Gaskins in view of Vaishampayan teaches the system of claim 12. Gaskins in view of Vaishampayan does not teach further comprising: a second plurality of temperature controllers individually configured to control a temperature of a second element within the semiconductor device; a second plurality of throttling tables, each throttling table of the second plurality of throttling tables corresponding to an individual temperature controller of the second plurality of temperature controllers; and a second central unit coupled with the second element and the second plurality of temperature controllers, the second central unit configured to dynamically control throttling steps applied to the second element by the individual temperature controllers of the second plurality of temperature controllers for thermal control of the semiconductor device.
However, Louie teaches further comprising:
a second plurality of temperature controllers individually configured to control a temperature of a second element within the semiconductor device (
Louie discloses, “In one aspect, the disclosure provides a distributed thermal management architecture. Accordingly, an apparatus for implementing thermal management, the apparatus including a serial databus; a central processing unit (CPU) coupled to the serial databus; a graphics processing unit (GPU) coupled to the serial databus; a neural signal processor (NSP) coupled to the serial databus; an always on subsystem (AOSS) coupled to the serial databus; wherein the serial databus, the CPU, the GPU, the NSP and the AOSS are implemented on a system on a chip (SOC); wherein the CPU includes a first plurality of thermal sensors and a first plurality of controllers, and each of the first plurality of thermal sensors is coupled to each of the first plurality of controllers; wherein the GPU includes a second plurality of thermal sensors and a second plurality of controllers, and each of the second plurality of thermal sensors is coupled to each of the second plurality of controllers,” ¶ 0004.
Here, Louie discloses more than 1 plurality of temperature controllers that each are configured to control their assigned element (CPU, GPU, etc.) within the system on a chip.);
and a second central unit coupled with the second element and the second plurality of temperature controllers, the second central unit configured to dynamically control throttling steps applied to the second element by the individual temperature controllers of the second plurality of temperature controllers for thermal control of the semiconductor (
Louie discloses, “In one example, the CPU further includes a first plurality of central broadcast (CB) units, wherein each of the first plurality of CB units is coupled to the each of the first plurality of controllers. In one example, each of the first plurality of controllers is configured to generate a digitized temperature data based on a thermal data received from the each of the first plurality of thermal sensors. In one example, the apparatus further includes a first plurality of local limit management (LLM) units, wherein each of the first plurality of LLM units is coupled to the each of the first plurality of CB units, and wherein each of the first plurality of LLM units is configured to execute a thermal management procedure based on whether the digitized temperature data has exceeded a predetermined thermal limit,” ¶ 0005, and “In one example, the apparatus further includes a second plurality of central broadcast (CB) units, wherein each of the second plurality of CB units is coupled to the each of the second plurality of controllers. In one example, each of the second plurality of controllers is configured to generate a digitized temperature data based on a thermal data received from the each of the second plurality of thermal sensors. In one example, the apparatus further includes a graphics management unit (GMU), wherein the GMU is coupled to the each of the second plurality of CB units, and wherein the GMU is configured to execute a thermal management procedure based on whether the digitized temperature data has exceeded a predetermined thermal limit,” ¶ 0006.
The claimed “second central unit” is mapped to the graphics management unit (GMU), which performs the same functionality for the GPU as the first plurality of local limit management units do for the CPU.
After the combination of Gaskins in view of Vaishampayan, with Louie, the individual temperature controllers of Louie are configured to apply throttling steps to the GPU, and the graphics management unit is also configured to dynamically control throttling steps applied to the GPU by its individual temperature controllers, as specified by Gaskins in view of Vaishampayan.).
Gaskins in view of Vaishampayan, and Louie are both considered to be analogous to the claimed invention because they are in the same field of computer thermal management. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Gaskins in view of Vaishampayan to incorporate the teachings of Louie and provide further comprising: a second plurality of temperature controllers individually configured to control a temperature of a second element within the semiconductor device, and a second central unit coupled with the second element and the second plurality of temperature controllers, the second central unit configured to dynamically control throttling steps applied to the second element by the individual temperature controllers of the second plurality of temperature controllers for thermal control of the semiconductor. Doing so would help provide improved simultaneous control over the temperature of two elements within the semiconductor device. (Louie discloses, “For example, the distributed thermal management system has thermal sensors routed to a plurality of thermal management controllers at several distributed locations,” ¶ 0032.).
Gaskins in view of Vaishampayan and Louie does not teach a second plurality of throttling tables, each throttling table of the second plurality of throttling tables corresponding to an individual temperature controller of the second plurality of temperature controllers.
However, Hermerding teaches a second plurality of throttling tables, each throttling table of the second plurality of throttling tables corresponding to an individual temperature controller of the second plurality of temperature controllers (
Hermerding discloses, “FIGS. 5-8 illustrate one embodiment of an implementation for a software reporting structure that may be used by a thermal management policy to determine which devices to thermally manage in a system. The software reporting structure may include one or more device power tables, one or more device throttle state tables, a device throttle control object, and one or more thermal influence tables,” ¶ 0044.
Here, multiple throttling tables (device throttle state tables) can be used. Said group of multiple throttling tables can be split into two subgroups, where one subgroup would
After the combination of Gaskins in view of Vaishampayan and Louie, with Hermerding, said group of multiple throttling tables can be split into two subgroups, where one subgroup would have each of its throttling tables be assigned to each of the controllers from Louie, and the other subgroup would have each of its throttling tables be assigned to each of the controllers from Gaskins in view of Vaishampayan.).
Gaskins in view of Vaishampayan and Louie, and Hermerding are both considered to be analogous to the claimed invention because they are in the same field of computer thermal management. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Gaskins in view of Vaishampayan and Louie to incorporate the teachings of Hermerding and provide a second plurality of throttling tables, each throttling table of the second plurality of throttling tables corresponding to an individual temperature controller of the second plurality of temperature controllers. Doing so would help allow for utilizing the multiple pluralities of throttling tables to perform more advanced throttling in order to more efficiently manage the temperature of more than one element.
Regarding Claim 16, Gaskins in view of Vaishampayan, Louie, and Hermerding teaches the system of claim 15, wherein the second central unit dynamically controls the throttling steps of the second plurality of temperature controllers based on a current performance state of the second element or a current throttling state of the second element (
Vaishampayan discloses, “If the thermal data is greater than a higher threshold, process 300 adjusts the GPU throttling table to increase the GPU throttling at block 308. In one embodiment, process 300 adjusts the GPU throttling table by throttling one or more of the different GPU utilizations for one, some, or all of the process priorities,” ¶ 0031, “In one embodiment, the receive thermal data module 602 receives the thermal data as described in FIG. 3, block 302 above. The compare higher thermal threshold module 604 compares the thermal data with a higher thermal threshold as described in FIG. 3, block 304 above. The compare lower thermal threshold 606 compares the thermal data with a lower thermal threshold as described in FIG. 3, block 306 above. The increase GPU throttling module 608 increases the GPU throttling for one or more processes as described in FIG. 3, block 308 above. The decrease GPU throttling module 610 decreases the GPU throttling for one or more processes as described in FIG. 3, block 310 above,” ¶ 0036.
After the combination of Gaskins in view of Vaishampayan, with Louie, the individual temperature controllers of Louie are configured to apply throttling steps to the GPU, the graphics management unit from Louie dynamically controls the throttling steps applied by its controllers based on thermal data as specified by Vaishampayan.).
Gaskins in view of Vaishampayan, and Louie are both considered to be analogous to the claimed invention because they are in the same field of computer thermal management. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Gaskins in view of Vaishampayan to incorporate the teachings of Louie and provide wherein the second central unit dynamically controls the throttling steps of the second plurality of temperature controllers based on a current performance state of the second element or a current throttling state of the second element. Doing so would help allow for greater and simultaneous control over the temperature of multiple elements of the semiconductor device.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Gaskins (US 20250068227 A1) in view of Vaishampayan (US 20150348226 A1) and Carbone (US 20150277454 A1).
Regarding Claim 14, Gaskins in view of Vaishampayan teaches the system of claim 12. Gaskins in view of Vaishampayan does not teach wherein the first central unit dynamically controls the throttling steps applied by the individual temperature controllers of the first plurality of temperature controllers based on a current throttling state of the first element.
However, Carbone teaches wherein the first central unit dynamically controls the throttling steps applied by the individual temperature controllers of the first plurality of temperature controllers based on a current throttling state of the first element (
Carbone discloses, “In some examples the throttle ratio parameter provides a ratio between the rate at which the first control loop 210 throttles an operating parameter of the first heat source and the rate at which the second control loop 212 throttles an operating parameter of the second heat source 260,” ¶ 0031, and “If the throttle ratio parameter specifies a M:N throttling relationship then the control loop manager 230 keeps track of the number of throttle steps implemented by each control loop and the number of throttle steps necessary to maintain the ratio. For example, if the throttle ratio specifies a 3:1 ratio between the first control loop 210 and the second control loop 212 then the control loop manager tracks the number of throttle steps implemented by the first control loop, and for every three steps implemented by the first control loop 210 the second control loop implements one throttle step.,” ¶ 0043.
Here, the throttling steps applied by a second control loop is based on the throttling steps of a first control loop. After the combination of Gaskins in view of Vaishampayan, with Carbone, these control loops would be replaced by the controllers of Gaskins in view of Vaishampayan.).
Gaskins in view of Vaishampayan, and Carbone are both considered to be analogous to the claimed invention because they are in the same field of computer thermal management. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Gaskins in view of Vaishampayan to incorporate the teachings of Carbone and provide wherein the central unit controls, via the second temperature controller, throttling steps applied to the element based on the application of throttling steps communicated by the first temperature controller. Doing so would help allow greater control of the temperature of the element by coordinating between the controllers (Carbone discloses, “Accordingly techniques for coordinating control loops for temperature control may find utility, e.g., in electronic devices,” ¶ 0003.).
Claims 17-18 are rejected under 35 U.S.C. 103 as being unpatentable over Vaishampayan (US 20150348226 A1) in view of Gaskins (US 20070116085 A1) and DeMoss (US 20230089174 A1).
Regarding Claim 17, Vaishampayan teaches a method for thermally controlling a semiconductor device, the method comprising:
receiving, at a first temperature controller, a current performance state of an element of the semiconductor device, the first temperature controller operatively coupled to the element (
Vaishampayan discloses, “In one embodiment, thermald 110 includes a GPU throttling module 600 that determines whether to selectively apply or relax a GPU throttle to a priority. In one embodiment, the GPU throttling module 600 includes a receive thermal data module 602, compare higher thermal threshold module 604, compare lower thermal threshold 606, increase GPU throttling module 608, and decrease GPU throttling module 610. In one embodiment, the receive thermal data module 602 receives the thermal data as described in FIG. 3, block 302 above,” ¶ 0036.);
controlling dynamically, via the first temperature controller, a throttling step of a plurality of throttling steps applied, via the first temperature controller, to the element, first temperature controller having access to the first throttling table (
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Vaishampayan discloses, “In one embodiment, the operating system 124 adjusts the operation of the GPU 106 to mitigate the thermal profile of the device 100. In this embodiment, the operating system 124 includes a thermal daemon (thermald) 110 and kernel 112. In this embodiment, thermald 110 is daemon that selectively throttles the GPU operations of one or more running processes in order to mitigate the thermal environment of the device 100,” ¶ 0026, and “FIG. 6 is a block diagram of one embodiment of a thermal daemon, thermald, 110 that manages GPU throttling based on the thermal data of the device. In one embodiment, thermald 110 includes a GPU throttling module 600 that determines whether to selectively apply or relax a GPU throttle to a priority,” ¶ 0036.
The claimed “first temperature controller” is mapped to the disclosed “thermald”, which controls the throttling of the GPU.).
Vaishampayan does not teach receiving, at a central unit, a current performance state of an element of the semiconductor device, the central unit operatively coupled to the element; controlling dynamically, via the central unit, a throttling step of a plurality of throttling steps applied, via a first temperature controller, to the element, the central unit operatively coupled to the first temperature controller, the first temperature controller configured to sequentially apply throttling steps to the element based on a first throttling table, the central unit having access to the first throttling table; and communicating, from the first temperature controller to the central unit, throttling steps applied to the element by the first temperature controller.
However, Gaskins teaches a central unit operatively coupled to the first temperature controller and an element (
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Gaskins discloses, “An integrated circuit (IC) according to an embodiment of the present invention includes a temperature sensor, configurable temperature profile logic, at least one controller, and temperature control logic,” ¶ 0009, and “In this case, the temperature control logic controls each controller to maintain the operating temperature value within either the maximum or the configured operating temperature range,” ¶ 0011.
The claimed “central unit” is mapped to the disclosed “temperature control logic”, which is coupled to and controls several controllers to maintain a temperature for an integrated circuit.
As can be seen in Gaskins’ figure, the temperature control logic is coupled to several temperature controllers 117, 119, 121, 123, and 125, and controls each of the controllers in order to maintain an operating temperature value.
This is consistent with the present application’s specification, which states that “In aspects, a central unit may be coupled with an element of the semiconductor device and one or more temperature controllers configured to sequentially apply throttling steps to the element to thermally control the element…,” ¶ 0023.
After the combination of Vaishampayan with Gaskins, Vaishampayan uses the temperature control logic from Gaskins, in order to control its own thermald for maintaining temperature of the GPU. Furthermore, the temperature control logic now receives the thermal data from the GPU via the thermald, and dynamically controls each of the throttling steps applied to the element. The temperature control logic now has access to the first throttling table via the thermald.).
Vaishampayan and Gaskins are both considered to be analogous to the claimed invention because they are in the same field of computer thermal management. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Vaishampayan to incorporate the teachings of Gaskins and provide receiving, at a central unit, a current performance state of an element of the semiconductor device, the central unit operatively coupled to the element; controlling dynamically, via the central unit, a throttling step of a plurality of throttling steps applied, via a first temperature controller, to the element, the central unit operatively coupled to the first temperature controller, the first temperature controller configured to sequentially apply throttling steps to the element based on a first throttling table, the central unit having access to the first throttling table. Doing so would help provide capabilities for adding more controllers for controlling the temperature more efficiently, with the central unit managing each controller. (Gaskins discloses, “The temperature control logic controls one or more controllers to maintain the operating temperature value within the configured operating temperature range,” ¶ 0009.).
Vaishampayan in view of Gaskins does not teach communicating, from the first temperature controller to the central unit, throttling steps applied to the element by the first temperature controller.
However, DeMoss teaches communicating, from the first temperature controller to the central unit, throttling steps applied to the element by the first temperature controller (
DeMoss discloses, “In some examples, the HDD performance management computing module 210 can perform the mitigation service at the information handling system 202 including providing a notification to a graphical user interface (GUI) 250 of the display device 214 indicating implementation of the mitigation service. For example, the notification can indicate the speed of the fan 216 is being reduced to, that the CPU 218 is being throttled, or both,” ¶ 0041.
Here, DeMoss’ HDD performance management computing module communicates a notification to a graphical user interface, indicating the degree to which a CPU is being throttled.
After the combination of Vaishampayan in view of Gaskins, with DeMoss, a notification would be sent from Vaishampayan’s claimed first temperature controller to Gaskins’s claimed central unit, and said notification would contain the degree to which Vaishampayan’s GPU is throttled, as specified by DeMoss.).
Vaishampayan in view of Gaskins, and DeMoss are both considered to be analogous to the claimed invention because they are in the same field of computer thermal management. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Vaishampayan in view of Gaskins to incorporate the teachings of DeMoss and provide communicating, from the first temperature controller to the central unit, throttling steps applied to the element by the first temperature controller. Doing so would help allow for the central unit to take further actions based on the notification, in order to improve performance (DeMoss discloses, “The notification can further indicate that further action can be taken in response to user input, such as the mitigation services, to mitigate the performance issues of the HDD 212,” ¶ 0041.).
Regarding Claim 18, Vaishampayan in view of Gaskins and DeMoss teaches the method of claim 17, wherein the dynamic control of the throttling step applied, via the first temperature controller, to the element is based on the current performance state of the element (
Vaishampayan discloses, “If the thermal data is greater than a higher threshold, process 300 adjusts the GPU throttling table to increase the GPU throttling at block 308. In one embodiment, process 300 adjusts the GPU throttling table by throttling one or more of the different GPU utilizations for one, some, or all of the process priorities,” ¶ 0031, “In one embodiment, the receive thermal data module 602 receives the thermal data as described in FIG. 3, block 302 above. The compare higher thermal threshold module 604 compares the thermal data with a higher thermal threshold as described in FIG. 3, block 304 above. The compare lower thermal threshold 606 compares the thermal data with a lower thermal threshold as described in FIG. 3, block 306 above. The increase GPU throttling module 608 increases the GPU throttling for one or more processes as described in FIG. 3, block 308 above. The decrease GPU throttling module 610 decreases the GPU throttling for one or more processes as described in FIG. 3, block 310 above,” ¶ 0036.).
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Vaishampayan (US 20150348226 A1) in view of Gaskins (US 20070116085 A1), DeMoss (US 20230089174 A1), and Hermerding (US 20060064999 A1).
Regarding Claim 19, Vaishampayan in view of Gaskins and DeMoss teaches the method of claim 17, further comprising:
controlling dynamically, by the central unit, a throttling step of a plurality of throttling steps applied, via a second temperature controller, to the element, the central unit operatively coupled to the second temperature controller, the second temperature controller configured to sequentially apply throttling steps to the element (
Vaishampayan discloses, “In one embodiment, the operating system 124 adjusts the operation of the GPU 106 to mitigate the thermal profile of the device 100. In this embodiment, the operating system 124 includes a thermal daemon (thermald) 110 and kernel 112. In this embodiment, thermald 110 is daemon that selectively throttles the GPU operations of one or more running processes in order to mitigate the thermal environment of the device 100,” ¶ 0026, and “FIG. 6 is a block diagram of one embodiment of a thermal daemon, thermald, 110 that manages GPU throttling based on the thermal data of the device. In one embodiment, thermald 110 includes a GPU throttling module 600 that determines whether to selectively apply or relax a GPU throttle to a priority,” ¶ 0036.
Gaskins discloses, “An integrated circuit (IC) according to an embodiment of the present invention includes a temperature sensor, configurable temperature profile logic, at least one controller, and temperature control logic,” ¶ 0009, “In this case, the temperature control logic controls each controller to maintain the operating temperature value within either the maximum or the configured operating temperature range,” ¶ 0011.
Here, multiple controllers maintain the operating temperature value of an integrated circuit. After the combination of Vaishampayan with Gaskins, the temperature control logic of Gaskins is now explicitly configured to dynamically control the throttling steps applied, for each controller, to the GPU as specified by Vaishampayan.);
and communicating, from the second temperature controller to the central unit, throttling steps applied to the element by the second temperature controller (
DeMoss discloses, “In some examples, the HDD performance management computing module 210 can perform the mitigation service at the information handling system 202 including providing a notification to a graphical user interface (GUI) 250 of the display device 214 indicating implementation of the mitigation service. For example, the notification can indicate the speed of the fan 216 is being reduced to, that the CPU 218 is being throttled, or both,” ¶ 0041.
Here, DeMoss’ HDD performance management computing module communicates a notification to a graphical user interface, indicating the degree to which a CPU is being throttled.
After the combination of Vaishampayan in view of Gaskins, with DeMoss, a notification would be sent from each of the multiple controllers from Vaishampayan in view of Gaskins, to Gaskins’s claimed central unit, and said notification would contain the degree to which Vaishampayan’s GPU is throttled, as specified by DeMoss.).
Vaishampayan and Gaskins are both considered to be analogous to the claimed invention because they are in the same field of computer thermal management. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Vaishampayan to incorporate the teachings of Gaskins and provide further comprising: controlling dynamically, by the central unit, a throttling step of a plurality of throttling steps applied, via a second temperature controller, to the element, the central unit operatively coupled to the second temperature controller, the second temperature controller configured to sequentially apply throttling steps to the element. Doing so would help provide capabilities for adding multiple controllers for controlling the temperature more efficiently, with the central unit managing each controller. (Gaskins discloses, “The temperature control logic controls one or more controllers to maintain the operating temperature value within the configured operating temperature range,” ¶ 0009.).
Vaishampayan in view of Gaskins, and DeMoss are both considered to be analogous to the claimed invention because they are in the same field of computer thermal management. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Vaishampayan in view of Gaskins to incorporate the teachings of DeMoss and provide communicating, from the second temperature controller to the central unit, throttling steps applied to the element by the second temperature controller. Doing so would help allow for the central unit to take further actions based on the notification, in order to improve performance (DeMoss discloses, “The notification can further indicate that further action can be taken in response to user input, such as the mitigation services, to mitigate the performance issues of the HDD 212,” ¶ 0041.).
Vaishampayan in view of Gaskins and DeMoss does not teach the second temperature controller configured to sequentially apply throttling steps to the element based on a second throttling table, the central unit having access to the second throttling table.
However, Hermerding teaches the second temperature controller configured to sequentially apply throttling steps to the element based on a second throttling table, the central unit having access to the second throttling table (
Hermerding discloses, “FIGS. 5-8 illustrate one embodiment of an implementation for a software reporting structure that may be used by a thermal management policy to determine which devices to thermally manage in a system. The software reporting structure may include one or more device power tables, one or more device throttle state tables, a device throttle control object, and one or more thermal influence tables,” ¶ 0044.
Here, multiple throttling tables (device throttle state tables) can be used.
After the combination of Vaishampayan in view of Gaskins and DeMoss, with Hermerding, each of the controllers from Vaishampayan in view of Gaskins and DeMoss would apply throttling steps based on its own assigned throttling table as specified by Hermerding. The temperature control logic (central unit) from Gaskins would also have access to each of the throttling tables.).
Vaishampayan in view of Gaskins and DeMoss, and Hermerding are both considered to be analogous to the claimed invention because they are in the same field of computer thermal management. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Vaishampayan in view of Gaskins and DeMoss to incorporate the teachings of Hermerding and provide the second temperature controller configured to sequentially apply throttling steps to the element based on a second throttling table, the central unit having access to the second throttling table. Doing so would help allow for utilizing the multiple throttling tables to perform more advanced throttling in order to more efficiently manage the temperature of the element.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Vaishampayan (US 20150348226 A1) in view of Gaskins (US 20070116085 A1), DeMoss (US 20230089174 A1), Hermerding (US 20060064999 A1), and Carbone (US 20150277454 A1).
Regarding Claim 20, Vaishampayan in view of Gaskins, DeMoss, and Hermerding teaches the method of claim 19. Vaishampayan in view of Gaskins, DeMoss, and Hermerding does not teach wherein the dynamic control of the throttling step applied, via the second temperature controller, to the element is based on the communicated throttling step previously applied by the first temperature controller.
However, Carbone teaches wherein the dynamic control of the throttling step applied, via the second temperature controller, to the element is based on the communicated throttling step previously applied by the first temperature controller (
Carbone discloses, “In some examples the throttle ratio parameter provides a ratio between the rate at which the first control loop 210 throttles an operating parameter of the first heat source and the rate at which the second control loop 212 throttles an operating parameter of the second heat source 260,” ¶ 0031, and “If the throttle ratio parameter specifies a M:N throttling relationship then the control loop manager 230 keeps track of the number of throttle steps implemented by each control loop and the number of throttle steps necessary to maintain the ratio. For example, if the throttle ratio specifies a 3:1 ratio between the first control loop 210 and the second control loop 212 then the control loop manager tracks the number of throttle steps implemented by the first control loop, and for every three steps implemented by the first control loop 210 the second control loop implements one throttle step.,” ¶ 0043.
Here, the throttling steps applied by a second control loop is based on the throttling steps of a first control loop. After the combination of Vaishampayan in view of Gaskins, DeMoss, and Hermerding, with Carbone, these control loops would be replaced by the controllers of Vaishampayan in view of Gaskins, DeMoss, and Hermerding.).
Vaishampayan in view of Gaskins, DeMoss, and Hermerding, and Carbone are both considered to be analogous to the claimed invention because they are in the same field of computer thermal management. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Vaishampayan in view of Gaskins, DeMoss, and Hermerding to incorporate the teachings of Carbone and provide wherein the dynamic control of the throttling step applied, via the second temperature controller, to the element is based on the communicated throttling step previously applied by the first temperature controller. Doing so would help allow greater control of the temperature of the element by coordinating between the controllers (Carbone discloses, “Accordingly techniques for coordinating control loops for temperature control may find utility, e.g., in electronic devices,” ¶ 0003.).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Ogawa (US 20160062340 A1): Temperature Management System, Temperature Management Method, and Non-Transitory Computer Readable Recording Medium Having Therein Program for Temperature Management
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/ANDREW NMN SUN/Examiner, Art Unit 2195
/KEVIN L YOUNG/Supervisory Patent Examiner, Art Unit 2194
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