DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
In the amendment filed August 19, 2026, claims 1, 4, 8, 11, 14, and 17 have been amended, claims 5 and 18 have been canceled, claims 20-22 have been added, claims 1-4, 6-17 and 19-22 are currently pending for examination.
Response to Arguments
Regarding 35 U.S.C. 102 and 103 applicant’s arguments, see pages 8 paragraphs 3 - page 9 paragraphs 1-2, filed August 19, 2026, with respect to claims 1-4, 6-10, 13-17 and 19 have been fully considered and are not persuasive.
Applicant’s arguments with respect to claim(s) 1-4, 6-10, 13-17 and 19 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Hence a new ground of rejection is further made in view of Roethin (US Pub. No.:2016/0261375).
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
Claims 1-4, 6-17 and 19-22 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 1 has been amended to recite in lines 5-6, " ... a second field used to identify the control word” . Neither the claim nor the specification further describe, " ... a second field used to identify the control word”. Paragraph 0031 of instant application disclose, “In this possible implementation, the control word may be followed by data content of the data. In other words, the first field and the second field in the control word may be used as a frame header of a data frame. After identifying the first field and the second field in the control word, the receive end may determine a start location of the data, to read the data from the bitstream. In this embodiment of this application, the first field and the second field in the control word are used as the frame header of the data frame, so that the frame header of the data frame does not need to be additionally set. This can simplify a design of a bitstream.” The claims and the specification of the instant application does not describe the method/step, " ... a second field used to identify the control word”.
Therefore claim 1 is rejected under 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement
The subject matter was not described in the specification (see paragraph 0014, 0030-0031, 0047, 0119) in such a way as to enable one skilled in the art to which it pertains, or with which it is most nearly connected, to make and /or use the invention.
Claims 8 and 14 are also rejected for the same reason as set forth above for claim 1.
Claims 2-4, 6-7, 9-13, 15-17, and 19-22 are also rejected since they are dependent on the rejected dependent claims 1, 8 and 14, respectfully, as set forth above.
Notice re prior art available under both pre-AIA and AIA
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3, 8, 14 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Kovacevic et al. (US Patent No.: 6674805), and further in view of Roethin (US Pub. No.:2016/0261375).
As per claim 1, Kovacevic disclose A method applied at a transmit end (see Fig. 4, Fig.5, a Framer 410 and Transport Packet Parser 420 (TPP)), the method comprising:
generating a bitstream (see Fig. 1, Fig.3, Fig.4, Fig.5, generating a transport packet stream), wherein the bitstream comprises data and a control word (see Fig. 1, a transport stream packet with a header and payload), and the control word comprises:
a first field indicating start location information of the control word (see Fig. 1, sync byte, see also Fig.3, Fig. 3, which discloses a header and packet data bytes (data), with the header including a packet start code prefix (first field claimed)),
a second field used to identify the control word (see Fig. 1, transport private data), and
a third field carrying link information indicating a wired serial link (see Fig. 1, payload unit start indicator, transport priority, PID which concern all information about the link { a wired serial link} and the payload, see also Fig.5, Fig.6, para. 6, 7, see also Fig.3, stream id, data alignment indicator or ES rate (third field claimed).) and
a fourth field indicating a PID location (see Fig.1, Fig.6, Fig.16, para. 85, video PID location 724, Fig.19, Fig.17, para. 88, 93, 129, 135, 203, PID indicating a lane number);
and sending the bitstream over the wired serial link configured to carry multiple lanes (see Fig.5, para. 6, 13, transmitting the bit stream over the bus 405 to buffer controller 460, that receives and stores the data payload based upon control signals).
Examiner Note: According to paragraph [0003] the problem to be solved by the present
application is to reduce complexity of a control signal. Moreover, paragraph [0073] reads: "one control word indicates multiple pieces of link information, and simplify a design at the physical layer.... Further, an amount of link information carried in the control word may be flexibly adjusted by flexibly adjusting the end location information of the control word, to provide flexibility of the control word". It is unclear in view of the formulation of the independent claims whether these claims miss essential features required to achieve the aforementioned technical effects, because they simply define a bitstream with a data and a
control field, such control field being formed of four fields which appear to be well-known in the art.
Although Kovacevic disclose a fourth field indicating a video PID location 724 as a lane number;
Kovacevic however does not explicitly disclose a fourth field indicating “a lane number”;
Roethin however disclose a fourth field indicating “a lane number” (see Fig.5, para. 0070-0072, in a first transmission mode 500, a packet of data provided to the PCS is of sufficient size that the PCS determines that the packet segmented for transmission in a number (N) of frames 502, 504, 506. The first frame 502 for transmission includes a part of the packet preceded by a start of packet (SOP) synchronization symbol 508. The part of the packet carried in the first frame 502 includes the packet header 510 and a first portion 512a of the data (Payload-1) provided in the packet, the second frame 504 includes data (Payload-2) 512a preceded by a continuation (CON) synchronization symbol 514a, and additional frames 506 may be transmitted as necessary. The final frame 506 may include a final portion of the data as Payload-N 512c with padding added as needed. The final frame 506 is preceded by a CON synchronization symbol 514b, with the CRC information 516 transmitted after the Payload-N 512c, see also Fig.7, Fig.8, para. 0090-0097, 0103-0110, inks may support a number (M) of lanes, where M>1, and where a link may be operated such that M PCS frames may be transmitted in a single PCS frame period. Various approaches to transmitting data over the multiple lanes are contemplated. An index (x), which can have a value 0≦x<M, is used to identity the M lanes as LANE.sub.x. In a first example, a set of PCS frames {N, N+1, N+2, . . . } are assigned to the M lanes such that PCS frame N is assigned to LANE.sub.0, PCS frame N+1 is assigned to LANE.sub.1 and so on until a PCS frame is assigned to each lane. In the next PCS frame interval, the PCS frame N+M can be assigned to LANE.sub.0, PCS frame N+M+1 is assigned to LANE.sub.1, etc. In other words, PCS frame X may be assigned to lane Y if (X modulo M)=Y, and in a second example, data is distributed across the M lanes at a byte level. Accordingly, adjacent bytes in a sequence of bytes for transmission can be assigned to adjacent lanes. The sequence of bytes are identified with the index N, N+1, N+2 etc. In this way, byte X may be transmitted on lane Y if (X modulo M)=Y / a fourth field indicating “a lane number”, see also para. 0014, a first lane, a second lane of the communication link, clearly a field indicating/identifying “a lane number”) and sending a bitstream over a wired serial link configured to carry multiple lanes (see para. 0059, 0098-0106, transmitting/sending a bitstream over communication link / a wired serial link configured to carry multiple lanes, see also Fig.1, para. 0040-0042, 0126, the control data bus 208 include wires that carry data).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to provide the functionality of a fourth field indicating “a lane number”, as taught by Roethin, in the system of Kovacevic, so the a communication link includes a plurality of lanes, and providing the frame of encoded data includes providing a first frame of encoded data for transmission on a first lane of the communication link, the first frame encoding a first received portion of a data packet to be transmitted on the communication link, providing a second frame of encoded data for transmission on a second lane of the communication link, the second frame encoding a second portion of the data packet that is received immediately after the first portion, indicated by “a lane number”, see Roethin, paragraph 14.
As per claim 3, the combination of Kovacevic and Roethin disclose the method according to claim 1.
Kovacevic further disclose wherein the first field and the second field indicate a receive end to perform frame delimitation on the data (see Fig.1, Fig.3, para. 6, the Framer 410 generates a signal labeled PACKET START to indicate the first byte of a packet, a start of frame and an end of frame used for frame delimitation on the data, see also para. 8, end of frame/signal).
As per claim 8, Kovacevic disclose A method applied at a receive end (see Fig. 1, Fig.3, Fig.4, Fig.5, buffer controller 460), the method comprising:
receiving a bitstream (see Fig.5, para. 6, 13, the Buffer controller 460 receives and stores the data payload based upon control signals received from the parsers / a bitstream), wherein the bitstream comprises data and a control word (see Fig. 1, header and payload), and the control word comprises:
a first field indicating start location information of the control word (see Fig. 1, sync byte),
a second field used to identify the control word (see Fig. 1, transport private data), and
a third field carrying link information indicating a wired serial link configured to carry multiple lanes (see Fig. 1, payload unit start indicator, transport priority, PID which concern all information about the link { a wired serial link} and the payload, see also Fig.5, para. 6); and
a fourth field indicating a PID location (see Fig.1, Fig.6, Fig.16, para. 85, video PID location 724, Fig.19, Fig.17, para. 88, 93, 129, 135, 203, PID indicating a lane number);
reading the control word from the bitstream based on the first field and the second field (see para. 7, 8, the Buffer controller 460 retrieves /reading the packet data {the first field and the second field} and stores it in a predefined memory location); and
reading the data from the bitstream based on the control word (see para. 10-12, the Buffer Controller 460 receiving / reading the video payload, information carried in the header of the video, retrieves the packet data and stores the data).
Although Kovacevic disclose a fourth field indicating a video PID location 724 as a lane number;
Kovacevic however does not explicitly disclose a fourth field indicating “a lane number”;
Roethin however disclose a fourth field indicating “a lane number” (see Fig.5, para. 0070-0072, in a first transmission mode 500, a packet of data provided to the PCS is of sufficient size that the PCS determines that the packet segmented for transmission in a number (N) of frames 502, 504, 506. The first frame 502 for transmission includes a part of the packet preceded by a start of packet (SOP) synchronization symbol 508. The part of the packet carried in the first frame 502 includes the packet header 510 and a first portion 512a of the data (Payload-1) provided in the packet, the second frame 504 includes data (Payload-2) 512a preceded by a continuation (CON) synchronization symbol 514a, and additional frames 506 may be transmitted as necessary. The final frame 506 may include a final portion of the data as Payload-N 512c with padding added as needed. The final frame 506 is preceded by a CON synchronization symbol 514b, with the CRC information 516 transmitted after the Payload-N 512c, see also Fig.7, Fig.8, para. 0090-0097, 0103-0110, inks may support a number (M) of lanes, where M>1, and where a link may be operated such that M PCS frames may be transmitted in a single PCS frame period. Various approaches to transmitting data over the multiple lanes are contemplated. An index (x), which can have a value 0≦x<M, is used to identity the M lanes as LANE.sub.x. In a first example, a set of PCS frames {N, N+1, N+2, . . . } are assigned to the M lanes such that PCS frame N is assigned to LANE.sub.0, PCS frame N+1 is assigned to LANE.sub.1 and so on until a PCS frame is assigned to each lane. In the next PCS frame interval, the PCS frame N+M can be assigned to LANE.sub.0, PCS frame N+M+1 is assigned to LANE.sub.1, etc. In other words, PCS frame X may be assigned to lane Y if (X modulo M)=Y, and in a second example, data is distributed across the M lanes at a byte level. Accordingly, adjacent bytes in a sequence of bytes for transmission can be assigned to adjacent lanes. The sequence of bytes are identified with the index N, N+1, N+2 etc. In this way, byte X may be transmitted on lane Y if (X modulo M)=Y / a fourth field indicating “a lane number”, see also para. 0014, a first lane, a second lane of the communication link, clearly a field indicating/identifying “a lane number”) and sending a bitstream over a wired serial link configured to carry multiple lanes (see para. 0059, 0098-0106, transmitting/sending a bitstream over communication link / a wired serial link configured to carry multiple lanes, see also Fig.1, para. 0040-0042, 0126, the control data bus 208 include wires that carry data).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to provide the functionality of a fourth field indicating “a lane number”, as taught by Roethin, in the system of Kovacevic, so the a communication link includes a plurality of lanes, and providing the frame of encoded data includes providing a first frame of encoded data for transmission on a first lane of the communication link, the first frame encoding a first received portion of a data packet to be transmitted on the communication link, providing a second frame of encoded data for transmission on a second lane of the communication link, the second frame encoding a second portion of the data packet that is received immediately after the first portion, indicated by “a lane number”, see Roethin, paragraph 14.
As per claim 14, Kovacevic disclose An apparatus (see Fig.4, Fig.5, a transport stream core), comprising:
a processor (see Fig.5, Framer 410/a CPU, a processor, see para. 6); and
a memory (see Fig.5, para. 7, TPP 420 with registers/ memory for storing) with instructions stored therein, wherein the instructions, when executed by the processor, enable the apparatus to
generate a bitstream (see Fig. 1, Fig.3, Fig.4, Fig.5, generating a transport packet stream), wherein the bitstream comprises data and a control word (see Fig. 1, a transport packet stream with header and payload), and the control word comprises:
a first field indicating start location information of the control word (see Fig. 1, sync byte),
a second field used to identify the control word (see Fig. 1, transport private data), and
a third field used to carry link information indicating a wired serial link (see Fig. 1, payload unit start indicator, transport priority, PID which concern all information about the link { a wired serial link} and the payload, see also Fig.5, para. 6); and
a fourth field indicating a PID location (see Fig.1, Fig.6, Fig.16, para. 85, video PID location 724, Fig.19, Fig.17, para. 88, 93, 129, 135, 203, PID indicating a lane number);
an interface (see Fig. 4, Fig. 5, TPP 420 with bus 405 interface) configured to send the bitstream over the wired serial link configured to carry multiple lanes (see Fig.5, para. 6, 13, transmitting the bit stream over the bus 405 to buffer controller 460, that receives and stores the data payload based upon control signals).
Although Kovacevic disclose a fourth field indicating a video PID location 724 as a lane number;
Kovacevic however does not explicitly disclose a fourth field indicating “a lane number”;
Roethin however disclose a fourth field indicating “a lane number” (see Fig.5, para. 0070-0072, in a first transmission mode 500, a packet of data provided to the PCS is of sufficient size that the PCS determines that the packet segmented for transmission in a number (N) of frames 502, 504, 506. The first frame 502 for transmission includes a part of the packet preceded by a start of packet (SOP) synchronization symbol 508. The part of the packet carried in the first frame 502 includes the packet header 510 and a first portion 512a of the data (Payload-1) provided in the packet, the second frame 504 includes data (Payload-2) 512a preceded by a continuation (CON) synchronization symbol 514a, and additional frames 506 may be transmitted as necessary. The final frame 506 may include a final portion of the data as Payload-N 512c with padding added as needed. The final frame 506 is preceded by a CON synchronization symbol 514b, with the CRC information 516 transmitted after the Payload-N 512c, see also Fig.7, Fig.8, para. 0090-0097, 0103-0110, inks may support a number (M) of lanes, where M>1, and where a link may be operated such that M PCS frames may be transmitted in a single PCS frame period. Various approaches to transmitting data over the multiple lanes are contemplated. An index (x), which can have a value 0≦x<M, is used to identity the M lanes as LANE.sub.x. In a first example, a set of PCS frames {N, N+1, N+2, . . . } are assigned to the M lanes such that PCS frame N is assigned to LANE.sub.0, PCS frame N+1 is assigned to LANE.sub.1 and so on until a PCS frame is assigned to each lane. In the next PCS frame interval, the PCS frame N+M can be assigned to LANE.sub.0, PCS frame N+M+1 is assigned to LANE.sub.1, etc. In other words, PCS frame X may be assigned to lane Y if (X modulo M)=Y, and in a second example, data is distributed across the M lanes at a byte level. Accordingly, adjacent bytes in a sequence of bytes for transmission can be assigned to adjacent lanes. The sequence of bytes are identified with the index N, N+1, N+2 etc. In this way, byte X may be transmitted on lane Y if (X modulo M)=Y / a fourth field indicating “a lane number”, see also para. 0014, a first lane, a second lane of the communication link, clearly a field indicating/identifying “a lane number”) and sending a bitstream over a wired serial link configured to carry multiple lanes (see para. 0059, 0098-0106, transmitting/sending a bitstream over communication link / a wired serial link configured to carry multiple lanes, see also Fig.1, para. 0040-0042, 0126, the control data bus 208 include wires that carry data).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to provide the functionality of a fourth field indicating “a lane number”, as taught by Roethin, in the system of Kovacevic, so the a communication link includes a plurality of lanes, and providing the frame of encoded data includes providing a first frame of encoded data for transmission on a first lane of the communication link, the first frame encoding a first received portion of a data packet to be transmitted on the communication link, providing a second frame of encoded data for transmission on a second lane of the communication link, the second frame encoding a second portion of the data packet that is received immediately after the first portion, indicated by “a lane number”, see Roethin, paragraph 14.
As per claim 16, claim 16 is rejected the same way as claim 3.
Claims 2, 4, 7, 9, 15 and 20-22 are rejected under 35 U.S.C. 103 as being unpatentable over Kovacevic et al. (US Patent No.: 6674805), in view of Roethin (US Pub. No.:2016/0261375) and further in view of Brewer (US Pub. No.: 2019/0243700).
As per claim 2, the combination of Kovacevic and Roethin disclose the method according to claim 1.
The combination of Kovacevic and Roethin however does not explicitly disclose wherein the link information comprises at least one of: a quantity of lanes for transmitting the bitstream, a power consumption status of hardware in the wired serial link, a working status of a circuit in the wired serial link, or a gain of a codec used in the wired serial link.
Brewer however disclose wherein a link information comprises at least one of: a quantity of lanes for transmitting the bitstream, a power consumption status of hardware in the wired serial link, a working status of a circuit in the wired serial link, or a gain of a codec used in the wired serial link (see Table 8 Fig.8, para. 0003, 0095, 0103, links support a number (M) of lanes, where M>1, as showing in table 8, 14 data lanes for transmitting bitstream).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to provide the functionality of wherein a link information comprises at least one of: a quantity of lanes for transmitting the bitstream, a power consumption status of hardware in the wired serial link, a working status of a circuit in the wired serial link, or a gain of a codec used in the wired serial link, as taught by Brewer, in the system of Kovacevic and Roethin, so as to determine a number of data lanes, see Brewer, paragraph 85.
As per claim 4, the combination of Kovacevic and Roethin disclose the method according to claim 1.
Kovacevic further disclose generating bitstream comprises generating bit streams over the interface (see para. 6, 10, generating the multi-streams video payload).
The combination of Kovacevic and Roethin however does not explicitly disclose the multiple bitstreams have a one-to-one correspondence to the multiple lanes; and sending the bitstream over the wired serial link comprises: sending the multiple bitstreams through the corresponding multiple lanes.
Brewer however disclose multiple bitstreams have a one-to-one correspondence to the multiple lanes; and sending the bitstream over the wired serial link comprises: sending the multiple bitstreams through the corresponding multiple lanes (see para. 0080-0091, the parallel data and control packet 200 and serial data and control packet 300 payload information is used to transport protocol information from fabric source EP circuitry 70 to destination EP circuitry 70 / the multiple bitstreams have a one-to-one correspondence to the multiple lanes, per para. 0095, sending the multiple bitstreams through the corresponding multiple lanes, all lanes = 14 bitstreams).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to provide the functionality of multiple bitstreams have a one-to-one correspondence to the multiple lanes; and sending the bitstream over the wired serial link comprises: sending the multiple bitstreams through the corresponding multiple lanes, as taught by Brewer, in the system of Kovacevic and Roethin, so as to determine a number of data lanes, see Brewer, paragraph 85.
As per claim 7, the combination of Kovacevic and Roethin disclose the method according to claim 1.
The combination of Kovacevic and Roethin however does not explicitly disclose wherein: the data comprises service data or training data; and in response to the data comprising training data, generating the bitstream comprises: adding the control word after the data to generate the bitstream.
Brewer however disclose wherein: a data comprises service data or training data (see Fig.5, para. 0065-0069, Fig.8, 0084, 0088, 0090-0092, link layer initialization includes determining the link configuration (width and frequency of link) for the serial protocol interface 350, training the communication link 75, and transitioning the communication link 75 to the active state, typically under the control of the controller 360 of the CPI circuit 100); and in response to the data comprising training data, generating the bitstream comprises: adding the control word after the data to generate the bitstream (see para. 0098-0103, 0112, a parallel data and control packet 200 is received from a parallel flit interface 425 and input into a decoder 414 and a series of multiplexers 420A, 420B, controlled by counter 422, with the multiplexers 420A, 420B and counter 422 clocked at the increased clock rate from the PLL 412. The multiplexers 420A, 420B select the various bits of the parallel data and control packet 200 to generate the sequence of 14 bit flits 305, 310, 315, 320, 325, 330, 335, and 340 of the serial data and control packet 300 for transmission by the transmitter 410A, see also para. 0114).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to provide the functionality of wherein: the data comprises service data or training data; and in response to the data comprising training data, generating the bitstream comprises: adding the control word after the data to generate the bitstream, as taught by Brewer, in the system of Kovacevic and Roethin, so as to determine a number of data lanes, see Brewer, paragraph 85.
As per claim 9, the combination of Kovacevic and Roethin disclose the method according to claim 8.
The combination of Kovacevic and Roethin however does not explicitly disclose further comprising: adjusting, based on the link information, at least one of: a power consumption status of hardware in the wired serial link, a working status of a circuit in the wired serial link, or a gain of a codec used in the wired serial link.
Brewer however disclose adjusting, based on the link information, at least one of: a power consumption status of hardware in the wired serial link, a working status of a circuit in the wired serial link, or a gain of a codec used in the wired serial link (see Fig.6, para. 0101-0107, adjusting, based on the link information a working status of a circuit in the wired serial link / the change in link state indicating a request to take the link inactive/or active).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to provide the functionality adjusting, based on the link information, at least one of: a power consumption status of hardware in the wired serial link, a working status of a circuit in the wired serial link, or a gain of a codec used in the wired serial link, as taught by Brewer, in the system of Kovacevic and Roethin, so as to determine a number of data lanes, see Brewer, paragraph 85.
As per claim 15, claim 15 is rejected the same way as claim 2.
As per claim 20, claim 20 is rejected the same way as claim 7.
As per claim 21, claim 21 is rejected the same way as claim 9.
As per claim 22, claim 22 is rejected the same way as claim 7.
Claims 6, 10, 13 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Kovacevic et al. (US Patent No.: 6674805), in view of Roethin (US Pub. No.:2016/0261375) and further in view of Meier (US Pub. No.: 2020/0374151).
As per claim 6, the combination of Kovacevic and Roethin disclose the method according to claim 1.
The combination of Kovacevic and Roethin however does not explicitly disclose wherein: the first field comprises multiple groups of same fields, and each group of fields comprises multiple bits; and the multiple groups of the same fields are configured to compensate for a difference between a clock cycle of the transmit end and a clock cycle of a receive end.
Meier however disclose wherein: a first field comprises multiple groups of same fields, and each group of fields comprises multiple bits; and the multiple groups of the same fields are configured to compensate for a difference between a clock cycle of the transmit end and a clock cycle of a receive end (see para. 0073-0084, the insertion of stuff-bits is used for the purpose of synchronization in asynchronous data transmission / compensate for a difference between a clock cycle of the transmit end and a clock cycle of a receive end. Also, the bit-stuffing algorithm (frame encoding) for the new transmission format is modified to the effect that a stuff-bit is inserted only after 10 consecutive bits with the same bus level, rather than after 5 bits. This means fewer overhead bits are needed in the data frame, which increases the efficiency of the data transmission / a first field comprises multiple groups of same fields, and each group of fields comprises multiple bits).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to provide the functionality of wherein: a first field comprises multiple groups of same fields, and each group of fields comprises multiple bits; and the multiple groups of the same fields are configured to compensate for a difference between a clock cycle of the transmit end and a clock cycle of a receive end, as taught by Meier, in the system of Kovacevic and Roethin, so as to provide a method for transmitting data over a serial communication bus, a correspondingly designed bus interface, see Meier, paragraphs 0022-0026.
As per claim 10, the combination of Kovacevic and Roethin disclose the method according to claim 8.
The combination of Kovacevic and Roethin however does not explicitly disclose wherein reading the data from the bitstream based on the control word comprises: determining a coding length of the control word based on the first field and the second field; identifying a frame start location of the data from the bitstream based on the coding length of the control word; and reading the data based on the frame start location of the data.
Meier however disclose wherein reading the data from the bitstream based on the control word comprises: determining a coding length of the control word based on the first field and the second field (see Fig.6, para. 0040, 0068, at least one end-of-frame code is entered in the end field, wherein the end-of-frame code has a length of 11 bits); identifying a frame start location of the data from the bitstream based on the coding length of the control word; and reading the data based on the frame start location of the data (see para. 0024, 0037, 0039, Fig.4, para. 0056, providing a start field in the transmission field; and packaging the data as an Ethernet transmission frame which is inserted into the data field of the modified transmission frame, wherein the arbitration field and the start field replace a preamble and a start frame delimiter of the Ethernet transmission frame. and reading the data based on the frame start location of the data).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to provide the functionality of wherein reading the data from the bitstream based on the control word comprises: determining a coding length of the control word based on the first field and the second field; identifying a frame start location of the data from the bitstream based on the coding length of the control word; and reading the data based on the frame start location of the data, as taught by Meier, in the system of Kovacevic and Roethin, so as to provide a method for transmitting data over a serial communication bus, a correspondingly designed bus interface, see Meier, paragraphs 0022-0026.
As per claim 13, the combination of Kovacevic and Roethin disclose the method according to claim 8.
Kovacevic further disclose the method further comprises: performing, based on a clock frequency offset between the receive end and a transmit end, one of the following operations: deleting at least one group of fields from the multiple groups of same fields, or adding at least one group of fields to the multiple groups of same fields (see Fig.1, Fig.3, para. 4, 6, 17, 27, 70, 280, the framer 410 provides an indicator when synchronization lock / a clock frequency offset is achieved to the transport stream by the framer 410. Once framer lock is achieved, the clock recovery module 490 is enabled to receive PCR data from the adaptation field parser 450. The register set 480 provides access to registers needed to control operation of the clock recovery module 490/ adding to the multiple groups of same fields).
The combination of Kovacevic and Roethin however does not explicitly disclose wherein: the first field comprises multiple groups of same fields, and each group of fields comprises multiple bits.
Meier however disclose wherein: the first field comprises multiple groups of same fields, and each group of fields comprises multiple bits end and performing, based on a clock frequency offset between the receive end and a transmit end, one of the following operations: deleting at least one group of fields from the multiple groups of same fields, or adding at least one group of fields to the multiple groups of same fields (see para. 0073-0084, the insertion of stuff-bits is used for the purpose of synchronization in asynchronous data transmission / add for a difference between a clock cycle of the transmit end and a clock cycle of a receive end. Also, the bit-stuffing algorithm (frame encoding) for the new transmission format is modified to the effect that a stuff-bit is inserted only after 10 consecutive bits with the same bus level, rather than after 5 bits. This means fewer overhead bits are needed in the data frame, which increases the efficiency of the data transmission / a first field comprises multiple groups of same fields, and each group of fields comprises multiple bits).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to provide the functionality of wherein: the first field comprises multiple groups of same fields, and each group of fields comprises multiple bits end and performing, based on a clock frequency offset between the receive end and a transmit end, one of the following operations: deleting at least one group of fields from the multiple groups of same fields, or adding at least one group of fields to the multiple groups of same fields, as taught by Meier, in the system of Kovacevic and Roethin, so as to provide a method for transmitting data over a serial communication bus, a correspondingly designed bus interface, see Meier, paragraphs 0022-0026.
As per claim 19, claim 19 is rejected the same way as claim 6.
Allowable Subject Matter
Claims 11-12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Meier (US Pub. No.: 2020/0145254) – see para. 0030, “The same applies to the use of the bit-stuffing method, which was also already used in the CAN 2.0 protocol and the CAN FD protocol. An noteworthy feature here is that the data transmission takes place asynchronously and to ensure the synchronization of the data transmitting station and data receiving station a resynchronization is performed according to a bit-stuffing rule, wherein the bit-stuffing rule is applied over the areas from the start field up to the end of the data field, wherein the number of the inserted stuff bits is entered in a section of the CRC field as a check. The insertion of a stuff bit forces an edge change on the bus, which is used in the CAN controller for resynchronization of the timer, which sets the sampling rate for the bit recovery when receiving data. A modified bit-stuffing rule is used in this case. The bit-stuffing algorithm (frame encoding) for the new transmission format is modified to the effect that a stuff-bit is inserted only after 10 consecutive bits with the same bus level, and not after 5 bits as in CAN 2.0 and CAN FD”.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LAKERAM JANGBAHADUR whose telephone number is (571)272-1335. The examiner can normally be reached on M-F 7 am - 4 pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ian Moore can be reached on 571-272-3085. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/LAKERAM JANGBAHADUR/
Primary Examiner, Art Unit 2469
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