DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 3-6, 8 and 9 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by De (US 2017/0147516).
Consider claim 1, De discloses a method comprising: receiving, by a block device driver, an instruction to read data from one or more storage devices; writing the data from the one or more storage devices to a first memory location in pinned memory accessible by a vector processor and one or more other processors directly over a data bus; performing, by the vector processor, one or more invertible transforms on the data at the first memory location; and copying the data from the first memory location in the pinned memory to a second memory location in main memory that is separate from the one or more storage devices, the second location in main memory not being accessible by the vector processor via the data bus, wherein the block device driver is configured to run on the vector processor or the one or more other processors (abstract, [0011], [0014], [0019]-[0021], [0026], [0027], [0036], [0037], [0042], [0044], [0048], a GPU is disclosed that can operate as a vector processor that uses a portion of GPU memory as a pinned memory buffer. Data that is operated on by the GPU can be retrieved from system memory 82 (one or more storage devices, [0021] states that the GPU can get data from system memory 82) and is stored in the pinned memory and written to data storage unit 100 (main memory) after processing the information. As shown in figure 1, the GPU can communicate with the first memory location through the bus between the GPU and the GPU memory and the GPU communicates with all the other memories through buses 62, 63, 64. Thus bus used to communicate between the GPU and GPU memory can’t be used to access the other memories.).
Consider claim 3, De discloses the method of claim 1, wherein the block device interface comprises a block device interface for a meta-device, the meta-device corresponding to the one or more storage devices (abstract, [0011], [0014], [0019], [0020], [0026], [0042], [0044], [0048]).
Consider claim 4, De discloses the method of claim 1, further comprising: providing the block device interface (Fig. 1-2, abstract, [0011], [0014], [0019], [0020], [0026], [0042], [0044], [0048]).
Consider claim 5, De discloses the method of claim 1, wherein performing, by a vector processor, one or more invertible transforms on the data comprises one or more of: 20decrypting; decoding; decompressing; un-deduplicating; or logging ([0019], [0020], [0041] and [0042]).
Claim 6 and 8-9 are the system claim of method claims 1, 3 and 5 above and are rejected in the same manner, the additional components described are taught in the cited sections along with in figures 1 and 2.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2 and 7 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by De (US 2017/0147516) in view of official notice.
Consider claim 2, De discloses the method of claim 1, De further teaches using GPU memory as pinned memory and in [0021] that various configurations and types of memory the GPU memory can be. But, De does not explicitly state that the GPU memory can be non-volatile. However, it is well-known that a memory can be either a specific type of non-volatile memory or effectively non-volatile by adding a batter back up to the memory. The examiner is taking official notice to this feature.
Therefore, it would have been obvious to a person of ordinary skill in the art at the time the invention was made for the GPU memory of De to be non-volatile because non-volatile memory holds data in the event of an unexpected power failure, thus improving system reliability.
Claim 7 is the system claims to method claim 2 and is rejected in the same manner.
Response to Arguments
Applicant's arguments filed 12/23/2025 have been fully considered but they are not persuasive. The applicant’s argues pertain to the new claim amendments, which have been addressed in the appropriate claim rejections above. The 103 rejection has been corrected. Only claims 2 and 7 should have been included under that heading.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL ALSIP whose telephone number is (571)270-1182. The examiner can normally be reached M-F 9-5.
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/MICHAEL ALSIP/Primary Examiner, Art Unit 2136