DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on July 18, 2024 was filed after the mailing date of the application on July 18, 2024. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The disclosure is objected to because of the following informalities: Applicant’s disclosure on p. 1 has a blank underline where it should instead recite “12,079,917”.
Appropriate correction is required.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-12 are rejected on the ground of nonstatutory double patenting as being unpatentable over Claims 1-12 of U.S. Patent No. 12,079,917; Claims 1-12 are rejected on the ground of nonstatutory double patenting as being unpatentable over Claims 1-12 respectively of U.S. Patent No. 11,688,123; Claims 1-12 are rejected on the ground of nonstatutory double patenting as being unpatentable over Claims 1-12 of U.S. Patent No. 11,276,222, as shown in the tables below. Although the claims at issue are not identical, they are not patentably distinct from each other because the instant application claims are broader in every aspect than the patent claims and are therefore an obvious variant thereof.
18/777,387
Claim 1
2
3
4
5
6
7
8
9
10
11
12
12,079,917
Claim 1
2
3
4
5
6
7
9
10
11
12
8
11,688,123
Claim 1
2
3
4
5
6
7
8
9
10
11
12
11,276,222
Claim 1
2
3
4
5
6
7
9
10
11
12
8
18/777,387 (Claim 1)
12,079,917 (Claim 1)
A method of rendering a scene in a graphics system, the method comprising:
A method of rendering a scene in a graphics system, the method comprising:
analysing a shader to determine whether the shader samples from memory at coordinates matching a current fragment location; and
analysing a shader used by a draw call within a current render to determine whether the shader samples from a buffer at coordinates matching a current fragment location; and
in response to determining that the shader does sample from the memory at coordinates matching a current fragment location, replacing an instruction that reads data from the memory at coordinates matching a current fragment location with an instruction that reads from registers.
in response to determining that the shader used by the draw call does sample from the buffer at coordinates matching a current fragment location, recompiling the shader to replace an instruction that reads data from the buffer at coordinates matching a current fragment location with an instruction that reads from the buffer at coordinates stored in registers.
18/777,387 (Claim 1)
11,688,123 (Claim 1)
A method of rendering a scene in a graphics system, the method comprising:
A method of rendering a scene in a graphics system, the method comprising:
analysing a shader to determine whether the shader samples from memory at coordinates matching a current fragment location; and
identifying a draw call within a current render, wherein the current render samples from one or more buffers; analysing a shader used by the draw call to determine whether the shader samples from the one or more buffers at coordinates matching a current fragment location; and
in response to determining that the shader does sample from the memory at coordinates matching a current fragment location, replacing an instruction that reads data from the memory at coordinates matching a current fragment location with an instruction that reads from registers.
in response to determining that the shader used by the draw call does sample from the one or more buffers at coordinates matching a current fragment location, recompiling the shader to replace an instruction that reads data from one of the one or more buffers at coordinates matching a current fragment location with an instruction that reads from the one or more buffers at coordinates stored in registers.
18/777,387 (Claim 1)
11,276,222 (Claim 1)
A method of rendering a scene in a graphics system, the method comprising:
A method of rendering a scene in a graphics system, the method comprising:
analysing a shader to determine whether the shader samples from memory at coordinates matching a current fragment location; and
identifying a first draw call within a current render, wherein the current render samples from one or more buffers; analysing at least a last shader in a series of shaders used by the first draw call to determine whether the last shader samples from the one or more buffers at coordinates matching a current fragment location; and
in response to determining that the shader does sample from the memory at coordinates matching a current fragment location, replacing an instruction that reads data from the memory at coordinates matching a current fragment location with an instruction that reads from registers.
in response to determining that the last shader used by the first draw call does sample from the one or more buffers at coordinates matching a current fragment location, recompiling the last shader to replace an instruction that reads data from one of the one or more buffers at coordinates matching a current fragment location with an instruction that reads from the one or more buffers at coordinates stored in on-chip registers.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1 and 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nystad (US 20120223947A1), Fleischer (US 20200356371A1), and Ebeid (US 20120257742A1).
As per Claim 1, Nystad teaches a method of rendering a scene in a graphics system (fragment shader will use the attribute values to render primitives to generate a set of render output values, representing a frame for display, [0166]). Nystad teaches causing the vertex shader to store one copy of each relevant output attribute value, which is then reused each time a subsequent graphics processing stage needs that value [0043]. Nystad teaches identifying cases where the outputs of the vertex shader will be identical, and then acts to store and reuse as required only one copy of each such identical vertex shader output attribute value [0045]. The subsequent graphics processing stages, such as the fragment shader, reuse the single stored vertex shaded output attribute value each time they are to process a copy of that vertex shaded output attribute value by using the same index into the vertex shaded output attribute values each time they are to process a copy of the output attribute value in question so that they will read the same entry from the stored vertex shaded output attribute values each time [0081]. Thus, Nystad teaches analysing a shader to determine whether the shader currently needs the value that was previously stored; and in response to determining that the shader does currently need the value that was previously stored, then it reads from the entry that stored the value that is currently needed [0043, 0045, 0081]. It would have been obvious to one of ordinary skill in the art that when the shader samples from memory at coordinates matching a current fragment location, then the previous fragment location matches the current fragment location, and so the value for the previous fragment location that was previously stored is needed for the current fragment location. Thus, Nystad teaches the method comprising: analysing a shader to determine whether the shader samples from memory at coordinates matching a current fragment location; and in response to determining that the shader does sample from the memory at coordinates matching a current fragment location, then it reads from the entry that stored the value for the previous fragment location that is needed for the current fragment location [0043, 0045, 0081].
However, Nystad does not teach in response to determining that the shader does sample from the memory at coordinates matching the current fragment location, replacing an instruction that reads data from the memory at coordinates matching a current fragment location with an instruction that reads from registers. However, Fleischer teaches the operations retain a value in the operand register from the previous instruction in the operand register for reuse. The operations reuse a value in the operand register as indicated by an operand specifier in one or more of a plurality of instructions. The value is a previous value loaded in the operand register by previous instructions [0088]. Thus, this teaching from Fleischer can be implemented into the device of Nystad so in response to determining that shader does sample from memory at coordinates matching a current fragment location, then it reads from entry in registers that stored the value for the previous fragment location that is needed for the current fragment location.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Nystad so that in response to determining that the shader does sample from the memory at coordinates matching a current fragment location, then it reads from the entry in registers that stored the value for the previous fragment location that is needed for the current fragment location because Fleischer suggests that this improves computing efficiencies and data processing [0017].
However, Nystad and Fleischer do not teach in response to determining that the shader does sample from the memory at coordinates matching the current fragment location, replacing an instruction that reads data from the memory at coordinates matching a current fragment location with an instruction that reads from registers. However, Ebeid teaches minimizing the number of load instructions required in every iteration by reusing values from the previous iteration that are still in the registers [0019]. Thus, it replaces an instruction that reads data from the memory with an instruction that reads from registers. Thus, this teaching from Ebeid can be implemented into the combination of Nystad and Fleischer so that in response to determining that the shader does sample from the memory at coordinates matching a current fragment location, replacing an instruction that reads data from the memory at coordinates matching a current fragment location with an instruction that reads from registers.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Nystad and Fleischer so that in response to determining that the shader does sample from the memory at coordinates matching the current fragment location, replacing an instruction that reads data from the memory at coordinates matching a current fragment location with an instruction that reads from registers because Ebeid suggests that loading data from the memory takes a long time, and thus minimizing the number of load instructions required in every iteration by reusing values from the previous iteration that are still in the registers will increase the processing speed [0006, 0019].
As per Claim 12, Nystad teaches non-transitory computer readable storage medium having stored thereon computer readable code configured to cause the method to be performed when the code is executed (technology described herein may accordingly suitably be embodied as computer program product for use with computer system, such implementation may comprise computer readable instructions fixed on non-transitory computer readable medium, [0185]).
Claim(s) 2-3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nystad (US 20120223947A1), Fleischer (US 20200356371A1), and Ebeid (US 20120257742A1) in view of Langtind (US 20170193691A1).
As per Claim 2, Nystad, Fleischer, and Ebeid are relied upon for the teachings as discussed above relative to Claim 1.
However, Nystad, Fleischer, and Ebeid do not teach wherein recompiling the shader further comprises: removing any instructions that calculate the coordinates matching a current fragment location. However, Langtind teaches wherein recompiling the shader further comprises: removing any instructions that are not to be processed (vertex shader is modified to remove the attributes that are not to be processed by the first vertex shading operation and then recompiled, [0089]). Since the combination of Nystad, Fleischer, and Ebeid teaches replacing an instruction that reads data from the memory at coordinates matching a current fragment location, as discussed in the rejection for Claim 1, this teaching from Langtind can be implemented into the combination of Nystad, Fleischer, and Ebeid so that any instructions that calculate the coordinates matching a current fragment location are replaced and are not to be processed, and so recompiling the shader further comprises: removing any instructions that calculate the coordinates matching a current fragment location.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Nystad, Fleischer, and Ebeid so that recompiling the shader further comprises: removing any instructions that calculate the coordinates matching a current fragment location because Langtind suggests that this removes instructions that are not to be processed, so that the shader only processes instructions that are necessary, which improves computing efficiency [0089].
15. As per Claim 3, Nystad teaches further comprising modifying one or more other shaders to omit any instructions that calculate or output parameters used only by instructions that have been removed (vertex shader compiler omits the code to perform the copy operation and instead records in meta-information associated with the vertex shader code that the particular vertex shader output (secondary) attribute is a direct copy of the particular vertex shader input (primary) attribute and which vertex shader input (primary) attribute it is a copy of, [0270]).
16. Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nystad (US 20120223947A1), Fleischer (US 20200356371A1), and Ebeid (US 20120257742A1) in view of Heirich (US 20060152509A1).
Nystad, Fleischer, and Ebeid are relied upon for the teachings as discussed above relative to Claim 1. The combination of Nystad, Fleischer, and Ebeid teaches wherein analysing a shader to determine whether the shader samples from the memory at coordinates matching a current fragment location, as discussed in the rejection for Claim 1.
However, Nystad, Fleischer, and Ebeid do not expressly teach analysing a shader to determine whether the shader samples from memory using screen space coordinates that correspond to the current fragment location. However, Heirich teaches that the shader samples from memory using screen space coordinates that correspond to the fragment location (each fragment’s position in the screen space coordinate system, [0032]; output of the shader program may be dependent upon parameters associated with the pixel fragment, such as screen position, [0034]). Thus, this teaching of screen space coordinates from Heirich can be implemented into the combination of Nystad, Fleischer, and Ebeid so that analysing a shader to determine whether the shader samples from the memory at coordinates matching a current fragment location comprises: analysing a shader to determine whether the shader samples from memory using screen space coordinates that correspond to the current fragment location.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Nystad, Fleischer, and Ebeid so analysing shader to determine whether shader samples from memory at coordinates matching a current fragment location comprises: analysing shader to determine whether shader samples from memory using screen space coordinates that correspond to current fragment location as suggested by Heirich. It is well-known in the art that using screen space coordinates in fragment shader allows developers to map pixel-perfect 2D effects directly to the display, which enables hardware-accelerated post-processing, screen-door transparency, and resolution-independent rendering techniques.
17. Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nystad (US 20120223947A1), Fleischer (US 20200356371A1), and Ebeid (US 20120257742A1) in view of Fam (US 20150070367A1).
Nystad, Fleischer, and Ebeid are relied on for teachings discussed relative to Claim 1.
However, Nystad, Fleischer, and Ebeid do not expressly teach wherein the shader is used by an initial draw call in a current render. However, Fam teaches wherein the shader is used by an initial draw call in a current render (each render phase includes draw calls 310, and where each draw-call includes shader programs 315, [0027]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Nystad, Fleischer, and Ebeid so shader is used by initial draw call in current render as suggested by Fam. It is well-known in the art draw call contains all information the graphics API needs to draw on screen, such as information about shaders.
18. Claim(s) 8-9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nystad (US 20120223947A1), Fleischer (US 20200356371A1), and Ebeid (US 20120257742A1) in view of Morgan (US007015909B1).
19. As per Claim 8, Claim 8 is similar in scope to Claim 1, except that Claim 8 is directed to a graphics system comprising a general purpose processor, wherein the general purpose processor comprises a driver, wherein the driver is configured to perform the method of Claim 1. However, Nystad, Fleischer, and Ebeid do not expressly teach a graphics system comprising a general purpose processor, wherein the general purpose processor comprises a driver, wherein the driver is configured to perform the method. However, Morgan teaches a graphics system comprising a general purpose processor, wherein the general purpose processor comprises a driver, wherein the driver is configured to perform the method (low-level driver 530 which is executed by the system CPU and facilitates all communication with graphics processor 540, col. 9, lines 50-53; driver 530 includes a run-time compiler that compiles 470 the shader, which can then be executed, col. 11, lines 53-55; execute software instructions to implement the graphics functionality described herein, col. 5, line 65-col. 6, line 1; shader fragments can be reused, col. 6, lines 61-63). Thus, Claim 8 is rejected under the same rationale as Claim 1 along with this additional teaching from Morgan.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Nystad, Fleischer, and Ebeid to include a graphics system comprising a general purpose processor, wherein the general purpose processor comprises a driver, wherein the driver is configured to perform the method as suggested by Morgan. It is well-known in the art to use a driver so that programmers can write standard, generic code for applications without having to tailor the software to every specific device.
20. As per Claim 9, the combination of Nystad, Fleischer, and Ebeid teaches modifying the shader to replace an instruction that reads data from the memory at coordinates matching a current fragment location with an instruction that reads from registers, as discussed in the rejection for Claim 1.
However, Nystad, Fleischer, and Ebeid do not expressly teach that the general purpose processor is configured, in response to receiving a trigger signal from the driver, to perform the method. However, Morgan teaches this limitation, as discussed in the rejection for Claim 8.
21. Claim(s) 10-11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nystad (US 20120223947A1), Fleischer (US 20200356371A1), Ebeid (US 20120257742A1), and Morgan (US007015909B1) in view of Langtind (US 20170193691A1).
Claims 10-11 are similar in scope to Claims 2-3 respectively, and therefore are rejected under the same rationale.
Allowable Subject Matter
22. Claims 5-6 are rejected under double patenting, but would be allowable if terminal disclaimers are filed and Claims 5-6 are rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
23. The prior art taken singly or in combination do not teach or suggest the combination of all the limitations of Claim 5 and base Claim 1, and in particular, do not teach wherein analysing a shader to determine whether the shader samples from memory at coordinates matching a current fragment location comprises: inspecting code in the shader to determine whether one of a predefined set of patterns is present within the code.
24. Prior art taken singly or in combination do not teach or suggest combination of all limitations of Claim 6 and base Claim 1, and in particular, do not teach analysing a shader to determine whether the shader samples from memory at coordinates matching a current fragment location comprises: inspecting code in the shader to determine whether a sample position used to sample from the memory is calculated in the shader using a screen-space transformation.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JONI HSU whose telephone number is (571)272-7785. The examiner can normally be reached M-F 10am-6:30pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kee Tung can be reached at (571)272-7794. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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JH
/JONI HSU/Primary Examiner, Art Unit 2611
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