DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Application Status
This office action is responsive to the Application No.:18/777,430 filed on 07/18/2024 (Priority Date: 09/23/2022).
This action has been made NON-FINAL.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 07/18/2024 is being considered by the examiner. A signed IDS is hereby attached.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-30 are rejected under 35 U.S.C. 103 as being unpatentable over Aila US 20040212614 in view of Wu, US20200098169.
Claim 1:
Aila discloses an apparatus for graphics processing (See Aila Abstract1) but failed to disclose depth buffer. Wu discloses this feature in paragraph 0009. It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have further modified Aila’s “a method and a system for enhanced visibility test” by the teachings of Wu’s “processing bins in the depth buffer being updated”, to thereby enable improved graphics processing by using depth binning, more effectively (See Wu Abstract). In addition, both of the references teach features that are directed to analogous art and they are directed to the same field of endeavor, such as graphics processing. This close relation between both of the references highly suggests an expectation of success.
As modified:
The combination of Aila and Wu discloses the following:
a memory (See Aila Paragraph 0021);
and a processor coupled to the memory (See Aila Paragraphs 0019-0021);
and, based at least in part on information stored in the memory (See Aila Paragraphs 0019-21), the processor is configured to:
perform a first pass for a plurality of primitives in a frame (See Aila Paragraph 00082), wherein to perform the first pass the processor (See Aila Paragraph 0008; 0019-0021) is configured to:
perform a first visibility test for each of the plurality of primitives to determine a first set of visible primitives (See Aila Figure 1, Item 11; Figure 2, Item 22; Paragraph 00153);
and rasterize the first set of visible primitives to generate a first set of rasterized primitives (See Aila Figure 1, Item 15; Paragraph 00174);
update a depth buffer (See Wu Paragraph 0009) based on the first set of rasterized primitives (See Aila Figure 1, Item 15; Paragraph 00175);
perform a second pass for the first set of visible primitives (See Aila Paragraph 00086), wherein to perform the second pass the processor (See Aila Paragraph 0008; 0019-0021) is configured to:
rasterize the first set of visible primitives to generate a second set of rasterized primitives (See Aila Figure 1, Item 15; Paragraph 00177);
and perform a second visibility test for each of the second set of rasterized primitives (See Aila Figure 2, Item 25; Paragraphs 0007-0008; 0015-0017; 00218) using the updated depth buffer (See Wu Paragraph 0009) to determine a set of rasterized visible primitives (See Aila Figure 2, Item 25; Paragraphs 0007-0008; 0015-0017; 00219);
and output an indication of the set of rasterized visible primitives (See Aila Paragraphs 0007-0008; 0015-0017; 0021).
Claim 2:
The combination of Aila and Wu discloses wherein to perform the first visibility test for each of the plurality of primitives to determine the first set of visible primitives (See Aila Paragraph 000810), the processor is configured to: perform the first visibility test for each of the plurality of primitives before a rasterization of the first set of visible primitives to generate the first set of rasterized primitives (See Aila Paragraph 000811).
Claim 3:
The combination of Aila and Wu discloses wherein the depth buffer comprises at least one of a low resolution Z (LRZ) depth buffer or a fine depth buffer (See Wu Paragraph 0009).
Claim 4:
The combination of Aila and Wu discloses wherein, to perform the first visibility test for each of the plurality of primitives (See Aila Figure 1, Item 11; Figure 2, Item 22; Paragraph 0015), the processor (See Aila Paragraph 0008; 0019-0021) is configured to: perform a triangle visibility test on the plurality of primitives in the frame to determine the first set of visible primitives (See Aila Paragraph 0019).
Claim 5:
The combination of Aila and Wu discloses wherein the triangle visibility test comprises at least one of: a view frustrum test; a backface cull test; or a scissor and zero pixel test (See Wu Paragraphs 0009; 0047).
Claim 6:
The combination of Aila and Wu discloses wherein, to perform the second visibility test for each of the second set of rasterized primitives (See Aila Figure 2, Item 25; Paragraphs 0007-0008; 0015-0017; 0021), the processor is configured to: perform a coarse level depth test (See Wu Paragraph 0009) on the second set of rasterized primitives to determine the set of rasterized visible primitives (See Aila Figure 2, Item 25; Paragraphs 0007-0008; 0015-0017; 002112).
Claim 7:
The combination of Aila and Wu discloses wherein the indication of the set of rasterized visible primitives (See Aila Figure 1, Item 15; Paragraph 0017) comprises at least one of: a first indication of updated visibility information; or a second indication of updated position data (See Aila Paragraph 001913).
Claim 8:
The combination of Aila and Wu discloses wherein the first pass comprises a first binning pass and the second pass comprises a second binning pass (See Wu Paragraphs 0039; 0061).
Claim 9:
The combination of Aila and Wu discloses wherein the processor is further configured to: store, prior to updating the depth buffer, at least one of a visibility information or a position data for each of the plurality of primitives from the first pass (See Aila Paragraph 001914).
Claim 10:
The combination of Aila and Wu discloses wherein, to output the indication of the set of rasterized visible primitives (See Aila Figure 1, Item 15; Paragraphs 0017-0021), the processor is configured to: store the indication of the set of rasterized visible primitives (See Aila Figure 1, Item 15; Paragraphs 0017-0021); or transmit the indication of the set of rasterized visible primitives (See Aila Figure 1, Item 15; Paragraphs 0017-0021).
Claim 11:
The combination of Aila and Wu discloses store the indication of the set of rasterized visible primitives (See Aila Figure 1, Item 15; Paragraph 001715) in at least one of a graphics processing unit (GPU) buffer, an on-chip buffer, or a system memory (See Aila Paragraphs 0019-0021).
Claim 12:
The combination of Aila and Wu discloses wherein the processor is further configured to: perform a bin rendering pass (See Wu Paragraphs 0039; 0061) for each of the set of rasterized visible primitives (See Aila Figure 2, Item 25; Paragraphs 0007-0008; 0015-0017; 0021), wherein the bin rendering pass (See Wu Paragraphs 0039; 0061) is performed after a storage of the indication of the set of rasterized visible primitives (See Aila Figure 2, Item 25; Paragraphs 0007-0008; 0015-0017; 0021).
Claim 13:
The combination of Aila and Wu discloses wherein the frame comprises at least one of a current frame (See Aila Paragraph 0021) or a previous frame in a set of frames for a scene associated with the graphics processing, wherein the previous frame is prior to the current frame in the set of frames (See Aila Paragraph 0021).
Claim 14:
The combination of Aila and Wu discloses wherein the frame (See Aila Paragraph 0021) comprises the current frame, wherein the first pass and the second pass are based on visibility information (See Aila Paragraph 001916) for each of the plurality of primitives in the previous frame (See Aila Paragraph 0021).
Claim 15:
The combination of Aila and Wu discloses wherein the frame is included in a scene associated with the graphics processing at a graphics processing unit (GPU), wherein the first pass and the second pass are performed by the GPU (See Wu Paragraph 0012-0013).
Claim 16:
The combination of Aila and Wu discloses wherein the apparatus comprises a wireless communication device (See Wu Paragraph 0012-0013).
Claims 17-29:
Claims 17-29 are rejected on the same basis as claims 1-10 and 13-15, respectively.
Claim 30:
Claim 30 is rejected on the same basis as claim 1.
Pertinent Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Seetharamaiah (US Patent No.: 9087410) discloses aspects of this disclosure relate to a method for rendering an image. For example, the method includes generating visibility information indicating visible primitives of the image. The method also includes rendering the image using a binning configuration, wherein the binning configuration is based on the visibility information.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHEREE N BROWN whose telephone number is (571)272-4229. The examiner can normally be reached M-F 5:30-2:00 PM EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, SAID BROOME can be reached at (571) 272-2931. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SHEREE N BROWN/Primary Examiner, Art Unit 2612 January 15, 2026
1 Aila’s Abstract recites “Present invention teaches a method and a system for enhanced visibility test in three-dimensional computer graphics. In the invention two separate visibility tests (22, 25) are applied. The visibility tests harness a Z-buffer (21). First test (22) is applied directly after geometry processing (20). After first test the occlusion information of the primitives is computed and stored to an occlusion buffer (24). The occlusion cache (24) may be compressed. The second visibility test (25) is applied for buffered primitives. Visible primitives are rasterized and moved to the frame buffer. The content of the frame buffer is displayed on the screen.”.
2 Aila Paragraph 0008 recites “all the primitives that have passed first visibility test are rasterized to the frame”.
3 Aila Paragraph 0015 recites “The first visibility test is performed in order of arriving from the geometry processor. The visibility is checked against already computed primitives.”
4 Aila Paragraph 0017 recites “the rasterization of the primitives.”
5 Aila Paragraph 0017 recites “the rasterization of the primitives.”
6 Aila Paragraph 0008 recites “all the primitives that have passed first visibility test are rasterized to the frame”.
7 Aila Paragraph 0017 recites “the rasterization of the primitives.”
8 Aila Paragraphs 0007-0008; 0015-0017; 0021 recites “after second visibility test all the visible primitives are rasterized.”
9 Aila Paragraphs 0007-0008; 0015-0017; 0021 recites “after second visibility test all the visible primitives are rasterized.”
10 Aila Paragraph 0008 recites “all the primitives that have passed first visibility test are rasterized to the frame”.
11 Aila Paragraph 0008 recites “all the primitives that have passed first visibility test are rasterized to the frame”.
12 Aila Paragraphs 0007-0008; 0015-0017; 0021 recites “after second visibility test all the visible primitives are rasterized.”
13 Aila Paragraph 0019 recites “The Z-buffer 21 stores visibility information.”
14 Aila Paragraph 0019 recites “The Z-buffer 21 stores visibility information.”
15 Aila Paragraph 0017 recites “the rasterization of the primitives.”
16 Aila Paragraph 0019 recites “The Z-buffer 21 stores visibility information.”