DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is in response to09/21/2026 Applicant’s Argument.
Claims 1-20 are pending and examined.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 6-7, 9, 14-15, 17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 7,656,734 to Thorp et al. (hereafter Thorp).
Regarding independent claim 1, Thorp teaches a memory device, comprising:
a heater device located on or in at least one die (i.e. heating elements physically distributed on-chip, see 2:38-39), the heater device comprising:
a switch element electrically connected to a power supply connection and the at least one die (FIG. 1: circuit implementing enable/disable function 124 coupled to supply voltage 104 and the on-chip elements as shown); and
a resistive element electrically connected to the switch element and a ground connection, the resistive element configured to generate heat at the memory device (FIG. 1: resistive heating elements 122A, 122B … 122N coupled to ground 112),
wherein the switch element is configured to switch between electrically connecting the at least one die to the power supply connection (if the thermal regulation circuit does not need to be activated as a result of step 304 in FIG. 3, the access memory is implicitly directly coupled to power supply 104 because function 124 of FIG. 1 is disabled) and connecting the resistive element to the power supply connection (if the thermal regulation circuit needs to be activated as a result of step 304 in FIG. 3, function 124 of FIG. 1 is enabled and resistive heating elements 122A, 122B … 122N are connected to supply voltage 104 via transistors 120A, 120B … 120N).
Regarding dependent claim 6, Thorp teaches wherein the heater device is separate and discrete from the at least one die in a redistribution layer (RDL) or an interposer operably coupled to the at least one die (because heating elements physically distributed on the memory IC, see 2:38-39).
Regarding dependent claim 7, Thorp teaches wherein the memory device comprises one or more of DRAM, NAND, or NOR die (see FIG. 3A and 4 of US 7,233,024 to Scheuerlein et al., which is incorporated by reference in Thorp).
Regarding dependent claim 9, Thorp implicitly teaches wherein the switch element comprises switching circuitry configured to be operated via one or more of an MRS command or a chip select command (FIG. 5: it is seen that MRS command or chip select command is required for the memory exiting a low power mode in step 506, and a thermal regulation circuit enabling in step 502).
Regarding dependent claims 14-15 and 17, see rejection applied to claims 6-7 and 9 above.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-4, 11-12 are rejected under 35 U.S.C. 103 as being unpatentable over Thorp.
Regarding dependent claim 2, Thorp teaches wherein the resistive element comprises: at least one first resistor having a first resistance (FIG. 1: resistive heating elements 122A); and at least one second resistor having a second resistance (FIG. 1: resistive heating elements 122B)
Thorp does not explicitly teach the second resistance is different than the first resistance. However, Thorp describes resistive heating elements may vary in number, heat up different parts of the IC, distributed on the same and/or different planes of memory arrays, controlled by different temperature sensors (see 3:57-4:11). This may suggest availability of design choice, and heating elements with different resistance values is considered design choice. For example, heating element of smaller resistance value may be needed to heat up a smaller part of the IC, and heating element of larger resistance value for larger part of the IC.
Regarding dependent claim 3, Thorp teaches wherein the heater device further comprises an additional switch element electrically connected to the switch element and the resistive element, the additional switch element configured to switch between electrically connecting the at least one first resistor to the switch element and connecting the at least one second resistor to the switch element (FIG. 1: transistors 120A and 120B corresponding to heating resistive elements 122A and 122B, respectively).
Regarding dependent claim 4, Thorp does not explicitly teach wherein the at least one first resistor has a resistance of about 4.0 ohms and the at least one second resistor has a resistance of about 24 ohms. However, as mentioned in rejection of claim 2, choosing the smaller heating element of 4 ohms, and larger heating element of 24 ohms may be a design choice.
Regarding dependent claims 11-12, see rejection applied to claims 2-3 above.
Claims 5, 10, 13 are rejected under 35 U.S.C. 103 as being unpatentable over Thorp in view of US 9,761,290 to Kankani et al. (hereafter Kankani).
Thorp teaches, as applied in prior rejection of claim 1, all claimed subject matter except further limitations set forth in the following claim(s).
Regarding dependent claim 5, Kankani teaches a chip package (see FIG. 6C) comprising heating elements wherein the heater device is located on or in an active surface of the at least one die peripheral to a memory array of the at least one die (FIG. 6B: heating resistor 610 are embedded within substrate 620).
Since Thorp and Kankani are both from the same field of endeavor, the purpose disclosed by Kankani would have been recognized in the pertinent art of Thorp.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to embed the heating elements within the substrate as taught by Kankani to the memory device of Thorp because it is a known design.
Regarding independent claim 10, Thorp teaches a memory device, comprising:
at least one die (memory chip/IC, see 2:38-39); and
a heater device operably coupled to the at least one die (i.e. heating elements physically distributed on the memory IC, see 2:38-39), the heater device comprising:
a resistive element electrically connected to a ground connection FIG. 1: resistive heating elements 122A, 122B … 122N coupled to ground 112), and
a switch element electrically connected to a power supply connection FIG. 1: circuit implementing enable/disable function 124 coupled to supply voltage 104),
wherein the switch element is configured to switch between electrically connecting the at least one die to the power supply connection if the thermal regulation circuit does not need to be activated as a result of step 304 in FIG. 3, the access memory is implicitly directly coupled to power supply 104 because function 124 of FIG. 1 corresponding to the at least die is disabled) and connecting the resistive element to the power supply connection if the thermal regulation circuit needs to be activated as a result of step 304 in FIG. 3, function 124 of FIG. 1 corresponding to the at least die is enabled and resistive heating elements 122A, 122B … 122N are connected to supply voltage 104 via transistors 120A, 120B … 120N).
Thorp does not teach the strike through limitations.
Kankani teaches a memory module comprising multiple memory devices (see FIG. 4A) operably coupled to a substrate (FIG. 6C: die 606 coupled to substrate 620). Heating elements are located within the substrate (FIG. 6B: heating resistor 610 are embedded within substrate 620, also see FIG. 5B). It is obvious that there must be connections to ground and power supply of the substrate in order to current a current flow through heating resistors.
Since Thorp and Kankani are both from the same field of endeavor, the purpose disclosed by Kankani would have been recognized in the pertinent art of Thorp.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to embed the heating elements within the substrate as taught by Kankani to the memory device of Thorp because it is a known design.
Regarding dependent claim 13, see rejection applied to claim 5 above.
Claims 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over Thorp in view of US 6,060,895 to Soh et al. (hereafter Soh).
Regarding independent claim 18, Thorp teaches a semiconductor structure, comprising:
FIG. 1: circuit 100) comprising:
a switch element electrically connected to a power supply connection (FIG. 1: circuit implementing enable/disable function 124 coupled to supply voltage 104)
a resistive element electrically connected to the switch element and a ground connection (FIG. 1: resistive heating elements 122A, 122B … 122N coupled to ground 112), the resistive element comprising:
at least one first resistor having a first resistance (FIG. 1: resistive heating elements 122A); and
at least one second resistor having a second, FIG. 1: resistive heating elements 122B),
wherein the switch element is configured to switch between electrically connecting the at least one die to the power supply connection (if the thermal regulation circuit does not need to be activated as a result of step 304 in FIG. 3, the access memory is implicitly directly coupled to power supply 104 because function 124 of FIG. 1 is disabled) and connecting the resistive element to the power supply connection (if the thermal regulation circuit needs to be activated as a result of step 304 in FIG. 3, function 124 of FIG. 1 is enabled and resistive heating elements 122A, 122B … 122N are connected to supply voltage 104 via transistors 120A, 120B … 120N).
Thorp does not explicitly teach the second resistance is different than the first resistance. However, Thorp describes resistive heating elements may vary in number, heat up different parts of the IC, distributed on the same and/or different planes of memory arrays, controlled by different temperature sensors (see 3:57-4:11). This may suggest availability of design choice, and heating elements with different resistance values is considered design choice. For example, heating element of smaller resistance value may be needed to heat up a smaller part of the IC, and heating element of larger resistance value for larger part of the IC.
Thorp does not teaches at least one wafer and a thermal and heat testing device located on or in the at least one wafer.
Soh teaches at least one wafer and a thermal and heat testing device located on or in the at least one wafer (see 4:12-5:16).
Since Thorp and Soh are both from the same field of endeavor, the purpose disclosed by Soh would have been recognized in the pertinent art of Thorp.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to implement the semiconductor structure of Thorp at wafer level of Soh to increasing reliability during manufacturing.
Regarding dependent claim 19, Thorp teaches wherein the heater device further comprises an additional switch element electrically connected to the switch element and the resistive element, the additional switch element configured to switch between electrically connecting the at least one first resistor to the switch element and connecting the at least one second resistor to the switch element (FIG. 1: transistors 120A and 120B corresponding to heating resistive elements 122A and 122B, respectively).
Allowable Subject Matter
Claims 8, 16 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
With respect to dependent claim 8: wherein the switch element comprises a fuse and a fuse device configured to selectively blow the fuse.
With respect to dependent claim 16: wherein the switch element comprises a fuse and a fuse device configured to selectively open the fuse.
With respect to dependent claim 20: wherein the at least one first resistor emulates an active power mode of a system in which the semiconductor structure is utilized, and wherein the at least one second resistor emulates a standby mode of the system.
Response to Arguments
Applicant's arguments filed 09/21/2026 have been fully considered and they are partially persuasive.
Finality of the Office Action is Premature
Applicant's request for reconsideration of the finality of the rejection of the last Office action is persuasive and, therefore, the finality of that action is withdrawn.
/Richard Elms/ 9/24/26 Supervisory Patent Examiner, Art Unit 2824
35 U.S.C. § 102(a)(l) Anticipation Rejections
a) Applicant argues:
PNG
media_image1.png
216
636
media_image1.png
Greyscale
In response to this argument, Examiner kindly directs Applicant to the following passages of Thorp:
Passage #1, column 2, lines 33-57:
PNG
media_image2.png
613
570
media_image2.png
Greyscale
Passage #2, column 9, lines 37-48:
PNG
media_image3.png
296
561
media_image3.png
Greyscale
Thorp describes an on-chip heating element in passage #1. The terms die and chip are often used interchangeably. Thorp further describes that an integrated circuit memory array may be a monolithic integrated circuit structure in passage #2, which is understood as a die. It appears that Thorp refers to the die as a chip or an IC.
Thorp, therefore, teaches limitation of claim 1.
b) Applicant argues:
PNG
media_image4.png
87
649
media_image4.png
Greyscale
In response to this argument, Examiner kindly points out that since the circuit 100 of FIG. 1 is an on-chip heating elements of a die, enable/disable function 124 coupling to the on-chip heating elements also means it coupling to the die.
Claims 1-7, 9-15, 17-19 maintain rejected for the reason set forth above.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VANTHU NGUYEN whose telephone number is (571)272-1881. The examiner can normally be reached M-F: 7:00AM - 3:00PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Richard Elms can be reached at (571) 272-1869. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
September 24, 2026
/VANTHU T NGUYEN/Primary Examiner, Art Unit 2824