DETAILED ACTION
Claims 16-29 are currently pending in the application. Cancelled claims 1-15 are original claims to patent US 9,335,953 B2 to Fujimoto et al. and claims 16-29 are newly added claims.
Notice of Pre-AIA or AIA Status
The present application is being examined under the pre-AIA first to invent provisions.
Reissue Applications
For reissue applications filed before September 16, 2012, all references to 35 U.S.C. 251 and 37 CFR 1.172, 1.175, and 3.73 are to the law and rules in effect on September 15, 2012. Where specifically designated, these are “pre-AIA ” provisions.
For reissue applications filed on or after September 16, 2012, all references to 35 U.S.C. 251 and 37 CFR 1.172, 1.175, and 3.73 are to the current provisions.
Applicant is reminded of the continuing obligation under 37 CFR 1.178(b), to timely apprise the Office of any prior or concurrent proceeding in which Patent No. 9,335,953 is or was involved. These proceedings would include any trial before the Patent Trial and Appeal Board, interferences, reissues, reexaminations, supplemental examinations, and litigation.
Applicant is further reminded of the continuing obligation under 37 CFR 1.56, to timely apprise the Office of any information which is material to patentability of the claims under consideration in this reissue application.
These obligations rest with each individual associated with the filing and prosecution of this application for reissue. See also MPEP §§ 1404, 1442.01 and 1442.04.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 16-29 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-13 of U.S. Patent No. 9,104,539 (herein Fujimoto ‘539) in view of U.S. Patent No. RE47,542 (herein Fujimoto ‘542). Although the claims at issue are not identical, they are not patentably distinct from each other because Fujimoto ‘539 and Fujimoto ‘542 contain the broadest reasonable interpretation of all of the limitations of the claims to be reissued. It would have been obvious to combine the claims of Fujimoto ‘539 and the teachings of Fujimoto ‘542 as one of ordinary skill in the art would have recognized the claims represent different scopes of the same disclosure.
Claim 16
Fujimoto ‘539 and Fujimoto ‘542
A memory system, comprising:
A memory device comprising:
(see Fujimoto ‘539 claim 1)
a nonvolatile semiconductor memory device accessed by a command from a host;
a nonvolatile semiconductor memory device;
(see Fujimoto ‘539 claims 1 and claim 9 discussing host access)
a control circuitry configured to control the nonvolatile semiconductor memory device;
a control section configured to control the nonvolatile semiconductor memory device;
(see Fujimoto ‘539 claim 1)
a memory serving as a work area connected to the control circuitry;
a memory serving as a work area connected to the control section;
(see Fujimoto ‘539 claim 1)
an extended function section to be controlled by the control circuitry; and
an extended function section to be controlled by the control section; and
(see Fujimoto ‘539 claim 1)
an extension register provided on the memory or on the control circuitry, the extension register being capable of defining an interface controlling an extended function of the extended function section, wherein
an extension register virtually provided on the memory or provided as hardware on the control section, the extension register being capable of defining an interface controlling an extended function of the extended function section, wherein
(see Fujimoto ‘539 claim 1)
the control circuitry processes a first command to read the extension register in units of predetermined data lengths, and a second command to write data to the extension register in units of predetermined data lengths,
the control section is arranged to process a first command to read data from the extension register in accordance with a designation of data length, and a second command to write data to the extension register in accordance with a designation of data length.
(see Fujimoto ‘539 claim 1)
the first command is received from the host,
(see Fujimoto ‘539 claims 9-13, host using/sending the first command to read information from the extension register)
the first command includes a first command number as an argument,
(see Fujimoto ‘539 claim 2, commands using number-based arguments/fields; additionally claim 1 indicates the first command is a read command and the second command is a write command, thus requiring differing “op codes” or “command numbers” argument/field)
the control circuitry sends a first response to the host in response to the first command,
(see Fujimoto ‘539 claims 9-13, host using the commands to access/read information)
the second command is received from the host,
(see Fujimoto ‘539 claims 11-13, host using the second command to access the extension register)
the second command includes a second command number as an argument, the second command number being different from the first command number,
(see Fujimoto ‘539 claim 2, commands using multiple number-based arguments/fields, with multiple differing types of arguments/fields, and differing values for those arguments/fields; additionally claim 1 indicates the first command is a read command and the second command is a write command, thus requiring differing “op codes” or “command numbers” argument/field)
the control circuitry sends a second response to the host in response to the second command, and
(see Fujimoto ‘539 claim 11, host access extension register via a second command; claim 7 indicates commands result in a response, and column 8, lines 52-62 shows the claimed second command results in a response to the host)
(see Fujimoto ‘542, claim 14, host using the commands to access and read information; claim 7 indicates commands result in a response; and column 6, line 65 to column 8, line 59, showing the claimed second command results in a response to the host)
the extension register includes a first area, and a second area different from the first area, wherein the first area records information specifying a type of the extended function and a controllable driver and address information indicating a place to which the extended function in the extension register is assigned and the second area records the extended function.
the extension register includes a first area, and a second area different from the first area, the first area is predetermined, the first area stores first information configured to specify a type of the extended function and a controllable driver, and address information indicating a place in the second area where second information for controlling the extended function is stored,
(see Fujimoto ‘539 claim 1)
Claim 17
(see Fujimoto ‘539 claim 2)
Claim 18
(see Fujimoto ‘539 claim 3)
Claim 19
(see Fujimoto ‘539 claim 4)
Claim 20
(see Fujimoto ‘539 claims 5, 9, 12)
Claim 21
(see Fujimoto ‘539 claim 6)
Claim 22
(see Fujimoto ‘539 claims 5, 6, 9, 12)
Claim 23
(see Fujimoto ‘539 claim 8)
Claim 24
(see Fujimoto ‘539 claim 9)
Claim 25
(see Fujimoto ‘539 claim 10)
Claim 26
(see Fujimoto ‘539 claim 7)
Claim 27
(see Fujimoto ‘539 claims 2, 11)
Claim 28
(see Fujimoto ‘539 claims 1, 12)
Claim 29
(see Fujimoto ‘539 claims 1, 6, 13)
Claims 16-29 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-25 of U.S. Patent No. RE47,542 (herein Fujimoto ‘542) in view of claims 1-13 of U.S. Patent No. 9,104,539 (herein Fujimoto ‘539). Although the claims at issue are not identical, they are not patentably distinct from each other because the claims of Fujimoto ‘542 and Fujimoto ‘539 contain the broadest reasonable interpretation of all of the limitations of the claims to be reissued. It would have been obvious to combine the claims of Fujimoto ‘542 and the claims of Fujimoto ‘539 as one of ordinary skill in the art would have recognized the claims represent different scopes of the same disclosure.
Claim 16
Fujimoto ‘542 and Fujimoto ‘539
A memory system comprising:
(see Fujimoto ‘542 claim 1)
a nonvolatile semiconductor memory device accessed by a command from a host;
(see Fujimoto ‘542 claims 1 and 10)
a control circuitry configured to control the nonvolatile semiconductor memory device;
(see Fujimoto ‘542 claim 1)
a memory serving as a work area connected to the control circuitry;
(see Fujimoto ‘539 claim 1)
an extended function section to be controlled by the control circuitry; and
(see Fujimoto ‘539 claim 1)
an extension register provided on the memory or on the control circuitry,
(see Fujimoto ‘542 claim 1; and Fujimoto ‘539 claim 1)
the extension register being capable of defining an interface controlling an extended function of the extended function section, wherein
(see Fujimoto ‘542 claim 1; and Fujimoto ‘539 claim 1)
the control circuitry processes a first command to read the extension register in units of predetermined data lengths, and a second command to write data to the extension register in units of predetermined data lengths,
(see Fujimoto ‘542 claim 1; and Fujimoto ‘539 claim 1)
the first command is received from the host,
(see Fujimoto ‘542 claims 1 and 14, host/using sending the first command for access)
(see Fujimoto ‘539 claims 9-13, host using/sending the first command to read information from the extension register)
the first command includes a first command number as an argument,
(see Fujimoto ‘542 claim 12, commands using number-based arguments/fields; additionally claim 1 indicates the first command is a read command and the second command is a write command, thus requiring differing “op codes” or “command numbers” argument/field)
(see Fujimoto ‘539 claim 2, commands using number-based arguments/fields; additionally claim 1 indicates the first command is a read command and the second command is a write command, thus requiring differing “op codes” or “command numbers” argument/field)
the control circuitry sends a first response to the host in response to the first command,
(see Fujimoto ‘542 claim 14, host using the first command to access and read information)
(see Fujimoto ‘539 claims 9-13, host using the commands to access/read information)
the second command is received from the host,
(see Fujimoto ‘542 claims 1 and 14, host using the first and second commands)
(see Fujimoto ‘539 claims 11-13, host using the second command to access the extension register)
the second command includes a second command number as an argument, the second command number being different from the first command number,
(see Fujimoto ‘542 claim 12, commands using multiple number-based arguments/fields, with multiple differing types of arguments/fields, and differing values for those arguments/fields; additionally claim 1 indicates the first command is a read command and the second command is a write command, thus requiring differing “op codes” or “command numbers” argument/field)
(see Fujimoto ‘539 claim 2, commands using multiple number-based arguments/fields, with multiple differing types of arguments/fields, and differing values for those arguments/fields; additionally claim 1 indicates the first command is a read command and the second command is a write command, thus requiring differing “op codes” or “command numbers” argument/field)
the control circuitry sends a second response to the host in response to the second command, and
(see Fujimoto ‘542 claim 14, host using the commands to access and read information; claim 7 indicates commands result in a response; and column 6, line 65 to column 8, line 59, showing the claimed second command results in a response to the host)
(see Fujimoto ‘539 claim 11, host access extension register via a second command; claim 7 indicates commands result in a response, and column 8, lines 52-62 shows the claimed second command results in a response to the host)
the extension register includes a first area, and a second area different from the first area, wherein the first area records information specifying a type of the extended function and a controllable driver and address information indicating a place to which the extended function in the extension register is assigned and the second area records the extended function.
(see Fujimoto ‘542 claim 1; and Fujimoto ‘539 claim 1)
Claim 17
(see Fujimoto ‘542 claim 2; and Fujimoto ‘539 claim 2)
Claim 18
(see Fujimoto ‘542 claim 3; and Fujimoto ‘539 claim 3)
Claim 19
(see Fujimoto ‘542 claim 4; and Fujimoto ‘539 claim 4)
Claim 20
(see Fujimoto ‘542 claim 5 and Fujimoto ‘539 claims 5, 9, 12)
Claim 21
(see Fujimoto ‘542 claim 6; and Fujimoto ‘539 claim 6)
Claim 22
(see Fujimoto ‘542 claim 6 and Fujimoto ‘539 claims 5, 6, 9, 12)
Claim 23
(see Fujimoto ‘542 claim 9; and Fujimoto ‘539 claim 8)
Claim 24
(see Fujimoto ‘542 claim 10; and Fujimoto ‘539 claim 9)
Claim 25
(see Fujimoto ‘542 claim 11; and Fujimoto ‘539 claim 10)
Claim 26
(see Fujimoto ‘542 claim 7; and Fujimoto ‘539 claim 7)
Claim 27
(see Fujimoto ‘542 claim 14)
Claim 28
(see Fujimoto ‘542 claim 15 and Fujimoto ‘539 claims 1, 12)
Claim 29
(see Fujimoto ‘539 claims 1, 6, 13)
Claims 16-29 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-27 of U.S. Patent No. RE48,997 (herein Fujimoto ‘997) in view of claims 1-13 of U.S. Patent No. 9,104,539 (herein Fujimoto ‘539). Although the claims at issue are not identical, they are not patentably distinct from each other because the claims of Fujimoto ‘997 and Fujimoto ‘539 contain the broadest reasonable interpretation of all of the limitations of the claims to be reissued. It would have been obvious to combine the claims of Fujimoto ‘997 and the claims of Fujimoto ‘539 as one of ordinary skill in the art would have recognized the claims represent different scopes of the same disclosure.
Claim 16
Fujimoto ‘997 and Fujimoto ‘539
A memory system comprising:
(see Fujimoto ‘997 claim 1)
a nonvolatile semiconductor memory device accessed by a command from a host;
(see Fujimoto ‘997 claim 1)
a control circuitry configured to control the nonvolatile semiconductor memory device;
(see Fujimoto ‘997 claim 1)
a memory serving as a work area connected to the control circuitry;
(see Fujimoto ‘539 claim 1)
an extended function section to be controlled by the control circuitry; and
(see Fujimoto ‘539 claim 1)
an extension register provided on the memory or on the control section,
(see Fujimoto ‘997 claim 1; and Fujimoto ‘539 claim 1)
the extension register being capable of defining an interface controlling an extended function of the extended function section, wherein
(see Fujimoto ‘997 claim 1; and Fujimoto ‘539 claim 1)
the control circuitry processes a first command to read the extension register in units of predetermined data lengths, and a second command to write data to the extension register in units of predetermined data lengths,
(see Fujimoto ‘997 claim 1; and Fujimoto ‘539 claim 1)
the first command is received from the host,
(see Fujimoto ‘997 claim 1, “host driver issues the first command”)
(see Fujimoto ‘539 claims 9-13, host using/sending the first command to read information from the extension register)
the first command includes a first command number as an argument,
(see Fujimoto ‘997 claim 16, commands using number-based arguments/fields; additionally claim 1 indicates the first command is a read command and the second command is a write command, thus requiring differing “op codes” or “command numbers” argument/field)
(see Fujimoto ‘539 claim 2, commands using number-based arguments/fields; additionally claim 1 indicates the first command is a read command and the second command is a write command, thus requiring differing “op codes” or “command numbers” argument/field)
the control circuitry sends a first response to the host in response to the first command,
(see Fujimoto ‘997 claim 1, first command to read, “host driver loads”)
(see Fujimoto ‘539 claims 9-13, host using the commands to access/read information)
the second command is received from the host,
(see Fujimoto ‘997 claims 1 and 16, second command)
(see Fujimoto ‘539 claims 11-13, host using the second command to access the extension register)
the second command includes a second command number as an argument, the second command number being different from the first command number,
(see Fujimoto ‘997 claim 16, commands using multiple number-based arguments/fields, with multiple differing types of arguments/fields, and differing values for those arguments/fields; additionally claim 1 indicates the first command is a read command and the second command is a write command, thus requiring differing “op codes” or “command numbers” argument/field)
(see Fujimoto ‘539 claim 2, commands using multiple number-based arguments/fields, with multiple differing types of arguments/fields, and differing values for those arguments/fields; additionally claim 1 indicates the first command is a read command and the second command is a write command, thus requiring differing “op codes” or “command numbers” argument/field)
the control circuitry sends a second response to the host in response to the second command, and
(see Fujimoto ‘997 claim 16, host access extension register via a second command; claim 21 indicates commands result in a response, and column 7, lines 1-64 shows the claimed second command results in a response to the host)
(see Fujimoto ‘539 claim 11, host access extension register via a second command; claim 7 indicates commands result in a response, and column 8, lines 52-62 shows the claimed second command results in a response to the host)
the extension register includes a first area, and a second area different from the first area, wherein the first area records information specifying a type of the extended function and a controllable driver and address information indicating a place to which the extended function in the extension register is assigned and the second area records the extended function.
(see Fujimoto ‘997 claim 1; and Fujimoto ‘539 claim 1)
Claim 17
(see Fujimoto ‘997 claim 16; and Fujimoto ‘539 claim 2)
Claim 18
(see Fujimoto ‘997 claim 17; and Fujimoto ‘539 claim 3)
Claim 19
(see Fujimoto ‘997 claim 18; and Fujimoto ‘539 claim 4)
Claim 20
(see Fujimoto ‘997 claims 19, 27; and Fujimoto ‘539 claims 5, 9, 12)
Claim 21
(see Fujimoto ‘997 claim 20; and Fujimoto ‘539 claim 6)
Claim 22
(see Fujimoto ‘997 claims 20, 23, 27; and Fujimoto ‘539 claims 5, 6, 9, 12)
Claim 23
(see Fujimoto ‘997 claim 25; and Fujimoto ‘539 claim 8)
Claim 24
(see Fujimoto ‘539 claim 9)
Claim 25
(see Fujimoto ‘997 claim 26; and Fujimoto ‘539 claim 10)
Claim 26
(see Fujimoto ‘997 claim 21; and Fujimoto ‘539 claim 7)
Claim 27
(see Fujimoto ‘997 claim 24)
Claim 28
(see Fujimoto ‘997 claim 27; and Fujimoto ‘539 claims 1, 12)
Claim 29
(see Fujimoto ‘539 claims 1, 6, 13)
Claims 16-29 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 16-26 of U.S. Patent No. RE50,101 (herein Fujimoto ‘101) in view of claims 1-13 of U.S. Patent No. 9,104,539 (herein Fujimoto ‘539). Although the claims at issue are not identical, they are not patentably distinct from each other because the claims of Fujimoto ‘101 and Fujimoto ‘539 contain the broadest reasonable interpretation of all of the limitations of the claims to be reissued. It would have been obvious to combine the claims of Fujimoto ‘101 and the claims of Fujimoto ‘539 as one of ordinary skill in the art would have recognized the claims represent different scopes of the same disclosure.
Claim 16
Fujimoto ‘101 and Fujimoto ‘539
A memory system comprising:
(see Fujimoto ‘101 claim 16)
a nonvolatile semiconductor memory device accessed by a command from a host;
(see Fujimoto ‘101 claim 1)
a control circuitry configured to control the nonvolatile semiconductor memory device;
(see Fujimoto ‘101 claim 1)
a memory serving as a work area connected to the control circuitry;
(see Fujimoto ‘539 claim 1)
an extended function section to be controlled by the control circuitry; and
(see Fujimoto ‘539 claim 1)
an extension register provided on the memory or on the control section,
(see Fujimoto ‘101 claim 1; and Fujimoto ‘539 claim 1)
the extension register being capable of defining an interface controlling an extended function of the extended function section, wherein
(see Fujimoto ‘101 claim 1; and Fujimoto ‘539 claim 1)
the control circuitry processes a first command to read the extension register in units of predetermined data lengths, and a second command to write data to the extension register in units of predetermined data lengths,
(see Fujimoto ‘101 claim 1; and Fujimoto ‘539 claim 1)
the first command is received from the host,
(see Fujimoto ‘101 claim 16, read command from host)
(see Fujimoto ‘539 claims 9-13, host using/sending the first command to read information from the extension register)
the first command includes a first command number as an argument,
(see Fujimoto ‘101 claim 16-21, commands using number-based arguments/fields; additionally claim 1 indicates the first command is a read command and the second command is a write command, thus requiring differing “op codes” or “command numbers” argument/field)
(see Fujimoto ‘539 claim 2, commands using number-based arguments/fields; additionally claim 1 indicates the first command is a read command and the second command is a write command, thus requiring differing “op codes” or “command numbers” argument/field)
the control circuitry sends a first response to the host in response to the first command,
(see Fujimoto ‘101 claim 16, read command reads data)
(see Fujimoto ‘539 claims 9-13, host using the commands to access/read information)
the second command is received from the host,
(see Fujimoto ‘539 claims 11-13, host using the second command to access the extension register)
the second command includes a second command number as an argument, the second command number being different from the first command number,
(see Fujimoto ‘539 claim 2, commands using multiple number-based arguments/fields, with multiple differing types of arguments/fields, and differing values for those arguments/fields; additionally claim 1 indicates the first command is a read command and the second command is a write command, thus requiring differing “op codes” or “command numbers” argument/field)
the control circuitry sends a second response to the host in response to the second command, and
(see Fujimoto ‘539 claim 11, host access extension register via a second command; claim 7 indicates commands result in a response, and column 8, lines 52-62 shows the claimed second command results in a response to the host)
the extension register includes a first area, and a second area different from the first area, wherein the first area records information specifying a type of the extended function and a controllable driver and address information indicating a place to which the extended function in the extension register is assigned and the second area records the extended function.
(see Fujimoto ‘101 claim 1; and Fujimoto ‘539 claim 1)
Claim 17
(see Fujimoto ‘101 claims 16-22; and Fujimoto ‘539 claim 2)
Claim 18
(see Fujimoto ‘101 claims 16-22; and Fujimoto ‘539 claim 3)
Claim 19
(see Fujimoto ‘101 claims 16-22; and Fujimoto ‘539 claim 4)
Claim 20
(see Fujimoto ‘101 claims 16-22; and Fujimoto ‘539 claims 5, 9, 12)
Claim 21
(see Fujimoto ‘101 claims 16-22; and Fujimoto ‘539 claim 6)
Claim 22
(see Fujimoto ‘101 claims 16-22; and Fujimoto ‘539 claims 5, 6, 9, 12)
Claim 23
(see Fujimoto ‘101 claim 24; and Fujimoto ‘539 claim 8)
Claim 24
(see Fujimoto ‘101 claim 23; and Fujimoto ‘539 claim 9)
Claim 25
(see Fujimoto ‘101 claim 25; and Fujimoto ‘539 claim 10)
Claim 26
(see Fujimoto ‘539 claim 7)
Claim 27
(see Fujimoto ‘101 claim 18; and Fujimoto ‘539 claim 2, 11)
Claim 28
(see Fujimoto ‘101 claim 26; and Fujimoto ‘539 claims 1, 12)
Claim 29
(see Fujimoto ‘539 claims 1, 6, 13)
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of pre-AIA 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(f) he did not himself invent the subject matter sought to be patented.
Claim 16 is/are rejected under pre-AIA 35 U.S.C. 102(f) because the applicant did not invent the claimed subject matter as compared to U.S. Patent No. 9,501,399 (herein Wakutsu ‘399).
Claim 16
Wakutsu ‘399
A memory system comprising:
A memory system comprising:
(see Wakutsu ‘399 claims 1 and 9)
a nonvolatile semiconductor memory device accessed by a command from a host;
a nonvolatile semiconductor memory;
(see Wakutsu ‘399 claims 1 and 9; and claim 10 discussing host access)
a control circuitry configured to control the nonvolatile semiconductor memory device;
a controller which controls the nonvolatile semiconductor memory;
(see Wakutsu ‘399 claims 1 and 9)
a memory serving as a work area connected to the control circuitry;
a memory serving as a work area of the controller;
(see Wakutsu ‘399 claims 1 and 9)
an extended function section to be controlled by the control circuitry; and
an extension register to be provided in the memory and including a plurality of pages, wherein the controller processes a first command to read data from the extension register in a unit of a page, and a second command to write data to the extension register in a unit of a page
(see Wakutsu ‘399 claims 1 and 9)
an extension register provided on the memory or on the control section, the extension register being capable of defining an interface controlling an extended function of the extended function section, wherein
an extension register to be provided in the memory and including a plurality of pages, wherein the controller processes a first command to read data from the extension register in a unit of a page, and a second command to write data to the extension register in a unit of a page
…
and wherein the extension register includes: a first register which indicates the wireless communication function to support; a second register for writing a third command to perform a wireless communication; a third register for reading a processing state of the third command; and a fourth register for reading an execution result of the third command.
(see Wakutsu ‘399 claims 1 and 9)
the control circuitry processes a first command to read the extension register in units of predetermined data lengths, and a second command to write data to the extension register in units of predetermined data lengths,
wherein the controller processes a first command to read data from the extension register in a unit of a page, and a second command to write data to the extension register in a unit of a page
(see Wakutsu ‘399 claims 1 and 9)
the first command is received from the host,
(see Fujimoto ‘399 claim 1, 9, 10, host using/sending the first command to read information from the extension register)
the first command includes a first command number as an argument,
(see Fujimoto ‘399 claim 1, 9, 10; see description of first and second commands, column 6, line 50 to column 8, line 43; commands using number-based arguments/fields; additionally claim 1 indicates the first command is a read command and the second command is a write command, thus requiring differing “op codes” or “command numbers” argument/field)
the control circuitry sends a first response to the host in response to the first command,
(see Fujimoto ‘399 claim 1, 9, 10; see description of first and second commands, column 6, line 50 to column 8, line 43)
the second command is received from the host,
(see Fujimoto ‘399 claim 1, 9, 10, host using/sending the second command)
the second command includes a second command number as an argument, the second command number being different from the first command number,
(see Fujimoto ‘399 claim 1, 9, 10; see description of first and second commands, column 6, line 50 to column 8, line 43; commands using multiple number-based arguments/fields, with multiple differing types of arguments/fields, and differing values for those arguments/fields; additionally claim 1 indicates the first command is a read command and the second command is a write command, thus requiring differing “op codes” or “command numbers” argument/field)
the control circuitry sends a second response to the host in response to the second command, and
(see Fujimoto ‘399 claim 1, 9, 10; see description of first and second commands, column 6, line 50 to column 8, line 43)
the extension register includes a first area, and a second area different from the first area, wherein the first area records information specifying a type of the extended function and a controllable driver and address information indicating a place to which the extended function in the extension register is assigned and the second area records the extended function.
wherein the extension register stores, in a specific page, information specifying the type of the wireless communication function and a driver capable of being controlled, and an address information indicating a region of the extension register to which the wireless communication function is assigned, wherein the extension register stores information of the wireless communication function in page different from the specific page
(see Wakutsu ‘399 claims 1 and 9)
Response to Arguments
Patent Owner's arguments filed 01/07/2026 have been fully considered but they are not persuasive. As the above Double Patenting rejections indicate, the amended claims still read upon the claims of 9,104,539, RE47,542, RE48,997, and RE50,101.
In view of the response of 01/07/2026 the following issues identified in the Office Action of 10/08/2025 are withdrawn: (1) the objections and rejections to the Declaration; (2) the objections to the Specification; and (3) and the double patenting rejection in view of US 9,501,399 B2.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/William H. Wood/
Reexamination Specialist, Art Unit 3992
Conferees:
/RACHNA S DESAI/Reexamination Specialist, Art Unit 3992
/ALEXANDER J KOSOWSKI/Supervisory Patent Examiner, Art Unit 3992