DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 16-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected group, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 12/7/2025.
Upon further review, Examiner has joined Group I and Group II for examination.
However, Applicant’s arguments as applied to claims 16-20 are not persuasive since the distinctions between claims 1-15 and claims 16-20 amount to vastly different search strategies. Claim 1 requires a specific relationship between the breakdown voltages of first and second transistors of a current mirror. Claim 16 requires a specific relationship between breakdown voltages of first and second transistors of a first amplifier compared to breakdown voltages of a plurality of high voltage elements, wherein the plurality of high voltage elements are not required to be in a current mirror configuration.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 13-15 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Miyajima (JP 2008129717A).
For claim 13, Miyajima teaches a method for operating an input buffer (Figure 4), comprising:
inputting a supply voltage (V1) at a first node where first (7) and second (6) transistors of a current mirror circuit are coupled with each other (top terminals of 6 and 7);
generating, by a current source (I1), a first current flowing through the first transistor (as understood by examination of Figure 4);
outputting, by the second transistor, in response to the supply voltage and the first current, a second current (current through 6), to generate a first voltage at a second node (node at bottom terminal of 6) between the current mirror circuit and a first amplifier (1, 2, 5, 9 and 10);
generating, in response to the first voltage, a third current flowing through a first path (4, 10, 2) and a fourth current flowing through a second path (3, 9, 1), wherein the first path and the second path are in parallel in the first amplifier and between the second node and a ground terminal (as understood by examination of Figure 4); and
generating a second voltage (voltage at top terminal of 2) and a third voltage (voltage at top terminal of 1) according to the third current and the fourth current (as understood by examination of Figure 4).
For claim 14, Miyajima further teaches:
the supply voltage is 2.2 to 2.5 volts ([36]).
For claim 15, Miyajima further teaches:
generating, by a second amplifier (3, 4), at least one fourth voltage in response to the second voltage and the third voltage (voltage at bottom terminal of 3 or voltage at bottom terminal of 4).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 3-9 and 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Miyajima (JP 2008129717A) in view of Tsai et al (US 2019/0140652).
For claim 1, teaches an input buffer (Figure 4), comprising:
a current mirror circuit (6, 7), comprising:
a first transistor (7) configured to be coupled with a current source (I1) at a first node (node coupled to bottom terminal of 7); and
a second transistor (6) coupled with the first transistor (two terminals are commonly connected, as understood by examination of Figure 4), and configured to output, according to a first current flowing through the first transistor, a second current at a second node (node coupled to bottom terminal of 6); and
a first amplifier (1, 2, 5, 9 and 10) coupled with the current mirror circuit at the second node, and comprising a first transistor pair (1, 2);
wherein the first transistor pair is configured to generate a first voltage (voltage at top terminal of 1) and a second voltage (voltage at top terminal of 2) in response to the second current, a first input voltage (voltage supplied as input to the gate of 2), and a second input voltage (voltage supplied as input to the gate of 1).
Miyajima fails to explicitly teach:
wherein a first breakdown voltage of the first transistor is smaller than a second breakdown voltage of the second transistor.
However, Tsai teaches “a first current mirror 210 including a transistor M.sub.0 and a transistor M.sub.1. Based on the principle of current mirror, a ratio of the first output current I.sub.1 passing through the transistor M.sub.1 to the input current I.sub.IN passing through the transistor M.sub.0 is a designated ratio…the current ratio I.sub.1/I.sub.IN can be determined by controlling a ratio of the size of the transistor M.sub.1 to the size of the transistor M.sub.0…” [19].
Before the effective filing date of the invention it would have been obvious to one of ordinary skill in the art to set the size of Miyajima’s first transistor to be smaller than that of the second transistor (and as a result, the first transistor having a smaller breakdown voltage than the second transistor) in order to adjust the current ratio.
Note, it has been held that the provision of adjustability, where needed, involves only routine skill in the art. In re Stevens 101 USPQ 284 (CCPA 1984).
Furthermore, the particular known technique (current ratio adjustment by adjusting transistor sizes) was recognized as part of the ordinary capabilities of one skilled in the art at the time of invention, as evidenced by Tsai.
For claim 3, the combination of Miyajima and Tsai teaches the limitations of claim 1 and Miyajima further teaches:
the first to second transistors are P-type transistors, and each transistor of the first transistor pair is an N-type transistor (as understood by examination of Miyajima’s Figure 4).
For claim 4, the combination of Miyajima and Tsai teaches the limitations of claim 1 and Miyajima further teaches:
a first terminal (bottom terminal) and a control terminal of the first transistor are coupled with each other at the first node (as understood by examination of Miyajima’s Figure 4).
For claim 5, the combination of Miyajima and Tsai teaches the limitations of claim 1 and Miyajima further teaches:
a control terminal of the first transistor and a control terminal of the second transistor are coupled with each other at the first node (as understood by examination of Miyajima’s Figure 4).
For claim 6, the combination of Miyajima and Tsai teaches the limitations of claim 1 and Miyajima further teaches:
a third breakdown voltage of the first transistor is larger than the first breakdown voltage (when a greater number of parallel transistors is selected than the number of parallel transistors corresponding to the first breakdown voltage, see rejection of claim 1 above).
For claim 7, the combination of Miyajima and Tsai teaches the limitations of claim 1 and Miyajima further teaches the first transistor pair comprises:
a third transistor (1) and a fourth transistor (2) that are coupled with each other in parallel between the second node and a ground terminal (as understood by examination of Figure 4).
For claim 8, the combination of Miyajima and Tsai teaches the limitations of claim 1 and Miyajima further teaches that the first amplifier further comprises:
a first resistor coupled with the third transistor in series (M9 functions as a variable resistor); and
a second resistor coupled with the fourth transistor in series (M10 functions as a variable resistor).
For claim 9, the combination of Miyajima and Tsai teaches the limitations of claim 8 and Miyajima further teaches:
the first resistor and the second resistor have a same resistance value ([43]).
For claim 12, the combination of Miyajima and Tsai teaches the limitations of claim 1 and Miyajima further teaches a second amplifier (3, 4), comprising:
a second transistor pair (3, 4) having control terminals coupled with the first amplifier (as understood by examination of Figure 4), wherein the second amplifier is configured to generate an output voltage (via 3), in response to the first voltage and the second voltage (as understood by examination of Figure 4).
Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Miyajima (JP 2008129717A) in view of Tsai et al (US 2019/0140652) and official notice.
For claim 2, the combination of Miyajima and Tsai teaches the limitations of claim 1 and Miyajima further teaches:
the first to second transistors are P-type transistors (as understood by the combination of references, see rejection of claim 1 above) but fails to teach each transistor of the first transistor pair are P-type transistors.
However, examiner takes official notice that it is notoriously old and well known that one having ordinary skill would know how to substitute PMOS for NMOS in a circuit and vice versa by, e.g., adapting the signal applied to the gate accordingly.
Before the effective filing date of the invention it would have been obvious to one of ordinary skill in the art to replace Miyajima’s M1 and M2 for equivalent PMOS transistors since the particular known technique was recognized as part of the ordinary capabilities of one skilled in the art.
Allowable Subject Matter
Claims 10-11 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL CALRISSIAN PUENTES whose telephone number is (571)270-5070. The examiner can normally be reached M-F 9-6:30 (flex).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Menatoallah Youssef can be reached at 571-270-3684. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DANIEL C PUENTES/Primary Examiner, Art Unit 2849