DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tsutsui et al. (US 5,922,623) in view of Joseph et al. (US 2015/0318182, cited by applicant) and Gagnon et al. (US 2021/0296124).
Regarding claim 1, Tsutsui teaches a method for processing a semiconductor substrate (figs. 1A-1C and 2), the method comprising: providing the semiconductor substrate (1-3) comprising a first layer (6) to be etched; exposing the semiconductor substrate to a gas-phase etchant and a process temperature ranging between 25-100°C to etch the first layer (col. 5, lines 13-44).
Tsutsui fails to teach depositing a second layer on the first layer and wherein the second layer deposited on the first layer increases an etch rate at which the first layer is etched, compare to an etch rate achieved without the second layer deposited on the first layer.
However, Joseph teaches depositing a second layer (coating of a hydrofluorocarbon polymer) on the first layer (substrate) and wherein the second layer deposited on the first layer increases an etch rate at which the first layer is etched, compared to an etch rate achieved without the second layer deposited on the first layer ([0042]-[0043], claims 4 and 5).
In view of Joseph’s teaching, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Tsutsui by incorporating the teaching as taught by Joseph so as to increase the etch rate (see Joseph: [0042]-[0043]).
Tsutsui as modified by Joseph fails to further teach the second layer comprising a metal oxide or metal fluoride material.
However, Gagnon teaches semiconductor substrate comprises plurality layers of different films such as zinc oxide [0040]).
In view of Gagnon’s teaching, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Tsutsui and Joseph by incorporating the teaching as taught by Gagnon in order to arrive at the claimed invention.
Regarding claim 2, Tsutsui as modified by Joseph and Gagnon teaches all subject matter claimed as applied above. Tsutsui, Joseph and Gagnon further teach wherein the first layer contains silicon (Tsutsui: col. 4, lines 56-61. Joseph: [0027], [0070] and Gagnon: [0040]).
Regarding claim 3, Tsutsui as modified by Joseph and Gagnon teaches all subject matter claimed as applied above. Joseph and Gagnon further teach wherein the first layer comprises silicon dioxide (SiO2) or silicon nitride (SiN) (Joseph: [0027] and [0031]. Gagnon: [0021] and [0040]).
Regarding claim 4, Tsutsui as modified by Joseph and Gagnon teaches all subject matter claimed as applied above. Gagnon further teaches wherein the second layer comprises aluminum oxide (Al2O3), gallium oxide (Ga2O3), hafnium oxide (HfO2), zinc oxide (ZnO), zirconium dioxide (ZrO2), aluminum fluoride (AlF3), gallium fluoride (GaF3), hafnium tetrafluoride (HfF4), zinc fluoride (ZnF2), or zirconium tetrafluoride (ZrF4) ([0040]).
Regarding claim 5, Tsutsui as modified by Joseph and Gagnon teaches all subject matter claimed as applied above. Joseph further teaches wherein a deposition thickness of the second layer ranges between 0.15nm and 1.5nm ([0030]).
Regarding claim 6, Tsutsui as modified by Joseph and Gagnon teaches all subject matter claimed as applied above. Joseph further teaches wherein the process temperature is within a range of 40-80°C during the exposing ([0052]).
Regarding claims 7-9, Tsutsui as modified by Joseph and Gagnon teaches all subject matter claimed as applied above except for controlling the etch rate as claimed. However, Joseph further different thicknesses can be selected to control the etch rate ([0055] and [0067]).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combinations of Tsutsui, Joseph and Gagnon to control the etch rate as claimed in order to arrive at the claimed invention.
Regarding claim 10, Tsutsui as modified by Joseph and Gagnon teaches all subject matter claimed as applied above. Joseph further teaches wherein said depositing the second layer on the first layer comprises depositing an aluminum oxide (Al2O3) layer on a silicon dioxide (SiO2) layer, and wherein a deposition thickness of the Al2O3 layer ranges between 0.15 nm and 1.5 nm ([0030]).
Regarding claim 11, Tsutsui as modified by Joseph and Gagnon teaches all subject matter claimed as applied above. Both Tsutsui and Joseph further teach wherein exposing the semiconductor substrate comprises exposing the semiconductor substrate to a gas-phase mixture of hydrogen fluoride (HF) and water (H2O) vapor and a process temperature ranging between 40-80°C, wherein the AI2O3 layer increases the etch rate of the SiO2 layer by providing a retention layer for HF and H2O, the retention layer providing a medium for more efficient reaction with a substrate of the SiO2 layer (Tsutsui: col. 5, lines 14-44. Joseph: [0027]).
Regarding claim 12, Tsutsui as modified by Joseph and Gagnon teaches all subject matter claimed as applied above. Joseph further teaches wherein the etch rate of the SiO2 layer ranges between 5 nanometers/minute (nm/min) and 25 nm/min ([0030] and [0052]).
Regarding claim 13, Tsutsui as modified by Joseph and Gagnon teaches all subject matter claimed as applied above. Joseph further teaches wherein the deposition thickness of the Al2O3 layer is approximately 1 nm, the process temperature is proximately 1 nm, the process temperature is approximately 60°C and the etch rate of the SiO2 layer is approximately 25 nm/min ([0030], [0052] and [0056]).
Regarding claim 14, Tsutsui teaches a method for processing a semiconductor substrate (figs. 1A-1C and 2), the method comprising: providing the semiconductor substrate (1-3), the semiconductor substrate comprising a first silicon-containing layer (6) to be etched; exposing the semiconductor substrate to a gas-phase etchant and a process temperature ranging between 25-100°C to etch portion of the first silicon-containing layer to form a pattern of features within the first silicon-containing layer (col. 5, lines 13-44).
Tsutsui fails to teach forming a patterned layer on the first silicon-containing layer and wherein the patterned layer formed on the first silicon-containing layer increases an etch rate at which the portions of first silicon-containing layer is etched, compared to an etch rate achieved in other portions of the first silicon-containing layer not covered by the patterned layer.
However, Joseph teaches forming a patterned layer (coating of a hydrofluorocarbon polymer) on the first layer (substrate) and wherein the patterned layer formed on the first silicon-containing layer increases an etch rate at which the portions of first silicon-containing layer is etched, compared to an etch rate achieved in other portions of the first silicon-containing layer not covered by the patterned layer ([0042]-[0043], claims 4 and 5).
In view of Joseph’s teaching, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Tsutsui by incorporating the teaching as taught by Joseph so as to increase the etch rate (see Joseph: [0042]-[0043]).
Tsutsui as modified by Joseph fails to further teach the patterned layer comprising a metal oxide or metal fluoride material.
However, Gagnon teaches semiconductor substrate comprises plurality layers of different films such as zinc oxide [0040]).
In view of Gagnon’s teaching, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Tsutsui and Joseph by incorporating the teaching as taught by Gagnon in order to arrive at the claimed invention.
Regarding claim 15, Tsutsui as modified by Joseph and Gagnon teaches all subject matter claimed as applied above. Joseph and Gagnon further teach wherein the first silicon-containing layer comprises silicon dioxide (SiO2) or silicon nitride (SiN) (Joseph: [0027] and [0031]. Gagnon: [0021] and [0040]).
Regarding claim 16, Tsutsui as modified by Joseph and Gagnon teaches all subject matter claimed as applied above. Gagnon further teaches wherein the patterned layer comprises aluminum oxide (Al2O3), gallium oxide (Ga2O3), hafnium oxide (HfO2), zinc oxide (ZnO), zirconium dioxide (ZrO2), aluminum fluoride (AlF3), gallium fluoride (GaF3), hafnium tetrafluoride (HfF4), zinc fluoride (ZnF2), or zirconium tetrafluoride (ZrF4) ([0040]).
Regarding claim 17, Tsutsui as modified by Joseph and Gagnon teaches all subject matter claimed as applied above. Joseph further teaches wherein a deposition thickness of the second layer ranges between 0.15nm and 1.5nm ([0030]).
Regarding claim 18, Tsutsui as modified by Joseph and Gagnon teaches all subject matter claimed as applied above. Joseph further teaches wherein the process temperature is within a range of 40-80°C during the exposing ([0052]).
Regarding claim 19, Tsutsui as modified by Joseph and Gagnon teaches all subject matter claimed as applied above except for an etch rate achieved in a second silicon-containing layer as claimed. However, Joseph further different compositions and thicknesses can be selected to increase the etch rate (claims 1, 4, [0055] and [0067]).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combinations of Tsutsui, Joseph and Gagnon to control the etch rate as claimed in order to arrive at the claimed invention.
Regarding claim 20, Tsutsui as modified by Joseph and Gagnon teaches all subject matter claimed as applied above. Tsutsui, Joseph and Gagnon further teach wherein the first silicon-containing layer silicon dioxide (SiO2) and the second silicon-containing layer comprises silicon (Si), silicon nitride (SiN) or silicon carbide (SiC) (Tsutsui: col. 4, lines 60-65. Joseph: [0027] and [0031]. Gagnon: [0021] and [0040]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
References: Gao et al. (US 2019/0237540); Park (US 2007/0114581); Shealy et al. (US 12,068,161); Lottes et al. (US 2024/0258155); Chang et al. (US 2023/0343598); Won et al. (US 2023/0057316) and Asako (US 2017/0062237) are cited because they are related to method for processing a semiconductor substrate.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Tuyen Kim Vo whose telephone number is (571)270-1657. The examiner can normally be reached Mon-Thurs: 8AM-6:30PM.
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/TUYEN K VO/ Primary Examiner, Art Unit 2876
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