DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-5, 8, 13-15 and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hampel et al. [US2021/0049115]. Hampel teaches memory controller for selective rank or subrank access.
Regarding claim 1, 3, 13, and 20, Hampel teaches a memory system [Hampel abstract “…a memory module…”], comprising:
a memory device [Hampel figure 9, feature 621 “memory module”], comprising:
a memory array comprising memory cells [Hampel figure 9, feature 623 “Memory Device A”]; and a peripheral circuit coupled to the memory array [Hampel figure 9, feature 607], wherein the peripheral circuit comprises a micro controller unit (MCU) [Hampel figure 9, feature 607 “memory controller”(Since the peripheral circuit comprises the micro controller unit then then the whole controller unit can be considered the peripheral circuit.)] and a plurality of circuits controlled by the MCU [Hampel figure 9, feature 610, 612, “MSel”, “SSel”, 615, 627, and 623 and 625 (The examiner has determined from the specification that circuits are defined in paragraph 0027 as “and other circuits controlled by the control logic 212, including a page buffer/sense amplifier 204, a column decoder/bit line driver 206, a row decoder/word line driver 208, and a voltage generator 210” and as such the examiner has determined this circuits to be inherently necessary for the typical operation of memory even though they are left out of the figure.)],
wherein the MCU is configured to switch between a first register [Hampel figure 9, feature 609 “TQueue”(Queues read on a type of register)] and a second register [Hampel figure 9, feature 611 “TQueue”] that are coupled to a first circuit of the plurality of circuits [Hampel figure 9, feature 623, 627, and 625], and wherein the peripheral circuit is configured to:
during a first time period [Hampel paragraph 0033, last lines “…the shared chip-select line may be activated to trigger sampling of the command/address path within the memory devices 301 of sub-rank A during a first command interval…”], send first data corresponding to a first operation from the MCU to the first register [Hampel paragraph 0046, middle lines “…The command path multiplexer 615 responds to a source-select value, SSel, to couple either internal command path 610 or internal command path 612 to command path, CA, and thus select either transaction queue 609 or transaction queue 611 to source the commands and associated address values for a given memory transaction…”]; and
during a second time period [Hampel paragraph 0033, middle lines “…to enable independent memory commands to be received within the A and B memory sub-ranks, a delay interval between chip-select line activation and sampling of the command/address paths—an interval referred to herein as a sampling latency—is established within the memory devices 303 of sub-rank B, so that command path sampling occurs at a later time within memory sub-rank B than within memory sub-rank A…”]:
perform the first operation by the first circuit [Hampel paragraph 0046, last lines “…the command path may be driven exclusively by one transaction queue or the other, with chip-select signals for memory sub-ranks (and the data input/output circuitry within transaction queues or elsewhere within the memory controller 607)…”]; and
send second data corresponding to a second operation from the MCU to the second register [Hampel paragraph 0046, middle lines “…after each command output sequence from a given transaction queue to enable the alternate transaction queue to drive command path CA in the ensuing command interval…”],
wherein the second operation is subsequent to the first operation [Hampel paragraph 0046, middle lines “…after each command output sequence from a given transaction queue…”(Where the word after reads on subsequent.)]; and
a controller coupled to the memory device and configured to send signals to the memory device to initiate the first operation and the second operation [Hampel 0003, last lines “…some time, T.sub.RD, after receipt of the memory access command, the read data values retrieved within each of the A and B memory devices are output in parallel data burst sequences…”].
Regarding claims 4 and 15, as per claim 1, Hampel teaches a multiplexer (MUX) is coupled between the first register and the second register [Hampel figure 9, feature 615], and wherein the MCU is configured to send an enable signal to the MUX to enable the switch between the first register and the second register [Hampel paragraph 0046, middle lines “…The command path multiplexer 615 responds to a source-select value, SSel, to couple either internal command path 610 or internal command path 612 to command path, CA, and thus select either transaction queue 609 or transaction queue 611 to source the commands and associated address values for a given memory transaction…”(Where the SSEL reads on the enable signal.)].
Regarding claims 5 and 15, as per claim 1, Hampel teaches the MCU is configured to send the enable signal to the MUX after the first time period and before the second time period [Hampel paragraph 0046, middle lines “…after each command output sequence from a given transaction queue to enable the alternate transaction queue to drive command path CA in the ensuing command interval…”].
Regarding claim 8, as per claim 1, Hampel teaches the MUX is coupled to an output terminal of the first register and an output terminal of the second register [Hampel figure 9, features 615, 610 and 612].
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 2 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Hampel et al. [US2021/0049115] in view of Pal et al. [US2016/0350112]. Hampel teaches memory controller for selective rank or subrank access. Pal teaches source operand read suppression for graphics processors.
Regarding claims 2 and 14, as per claim 1, Hampel fails to explicitly teach an address of the first register is same as an address of the second register.
However, Pal does teach a peripheral device with a first and second register where the address of the first register is same as an address of the second register [Pal paragraph 0044, first lines , “…Continuing to block 320, “first register address the same as second register address?” the processor may determine whether the first register address is the same as the second register address. For example, the processor may determine whether the register address 213-1 is the same as the register address 213-2…”(Pal shows that it was known in the art for both registers to have the same address.)].
Hampel and Pal are analogous arts in that they both deal with improving data access.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Hampel’s first and second registers with Pal’s teachings of the addresses for both registers being the same for the benefit of reducing resource consumption [Pal paragraph 0030, last lines “…may suppress the redundant reads (e.g., reads to the same register address) and also replicate the data read from the registers corresponding to the suppressed reads to prevent duplicate reads to the same register address, for example, to reduce resource consumption…”].
Allowable Subject Matter
Claims 6-7, 10-12, and 16-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Phillips et al. [US2002/0085497] Phillips teaches dual triggered registers for DMA access and register pairs as well.
Akiyama et al. [US2025/0085895] Akiyama teaches multiple FIFO registers coupled to a MUX for selection.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC CARDWELL whose telephone number is (571)270-1379. The examiner can normally be reached on Monday - Friday 10-6pm EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Reginald Bragdon can be reached on (571) 272-4204. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ERIC CARDWELL/Primary Examiner, Art Unit 2139