Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claim Interpretation - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
Claim limitation 10, 11, 12, has/have been interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because it uses/they use a generic placeholder interrupt transfer unit, inter-core communication unit, timer service unit, coupled with functional language without reciting sufficient structure to achieve the function. Furthermore, the generic placeholder is not preceded by a structural modifier. Since the claim limitation(s) invokes 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, claim 13 has/have been interpreted to cover the corresponding structure described in the specification that achieves the claimed function, and equivalents thereof.
A review of the specification, Fig. 8 [0092] shows that the following appears to be the corresponding structure described in the specification for the 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph limitation.
If applicant wishes to provide further explanation or dispute the examiner’s interpretation of the corresponding structure, applicant must identify the corresponding structure with reference to the specification by page and line number, and to the drawing, if any, by reference characters in response to this Office action.
If applicant does not intend to have the claim limitation(s) treated under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112 , sixth paragraph, applicant may amend the claim(s) so that it/they will clearly not invoke 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, or present a sufficient showing that the claim recites/recite sufficient structure, material, or acts for performing the claimed function to preclude application of 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
For more information, see MPEP § 2173 et seq. and Supplementary Examination Guidelines for Determining Compliance With 35 U.S.C. 112 and for Treatment of Related Issues in Patent Applications, 76 FR 7162, 7167 (Feb. 9, 2011).
Claim Rejections - 35 USC §103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim/s 1, 3, 10, 12, 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bai (Pub. No. US 2025/0028552) in view of Tsirkin (Pub. No. US 2024/0086219).
Claim 1, 10, 20, Bai teaches “an inter-core communication method comprising: transmitting, with respect to at least one interrupt pass-through core configured for an interrupt pass-through mode among a plurality of cores a physical interrupt directly to a client without going through a Hypervisor in response to the physical interrupt occurring, the Hypervisor being a virtual machine manager ([0071] Virtual machine monitor (VMM): is software, firmware, or hardware, for example, a hypervisor, used to create and run a virtual machine. [0257] memory, processor); and performing communication between the plurality of cores using a Fast Interrupt Request (FIQ) ([0112] According to the inter-application communication method in this embodiment of this application, the first virtual apparatus writes the first command into the first command queue based on the first request sent by the first application, and outputs the first inter-core interrupt to the core in which the second virtual apparatus is located, so that the second virtual apparatus is capable of obtaining the first inter-core interrupt and obtaining, based on the first inter-core interrupt, the first command from the first command queue, thereby implementing communication between the first virtual apparatus and the second virtual apparatus. The first command is written based on the first request from the first application, and includes the identifier of the second application on the second virtual apparatus, so that the second virtual apparatus is capable of running the second application based on the identifier that is of the second application and that is in the first command, thereby implementing communication between the application of the first virtual apparatus and the application of the second virtual apparatus. One of the first virtual apparatus and the second virtual apparatus is the virtual machine, and the other is the physical machine. Therefore, communication between the physical machine and the virtual machine is completed by directly outputting an inter-core interrupt to a core in which an object that needs to be communicated with is located, so that a virtual interrupt controller can be avoided to be used, thereby avoiding virtual machine entry/exit, implementing fast communication between a service of the virtual machine and a service of the physical machine, and improving communication efficiency of the electronic device. [0128] Based on this, the inter-application communication method in this embodiment of this application can implement inter-core interrupt receiving/sending when the virtual interrupt controller is disabled. Because the virtual interrupt controller is disabled, both an inter-core interrupt sent by the first virtual apparatus side and an inter-core interrupt sent by the second virtual apparatus side may be directly sent to an entity that is running when the inter-core interrupt is received. [0256] The processor 110 may include one or more processing units. For example, the processor 110 may include an application processor (AP), a modem processor, a graphics processing unit (GPU), an image signal processor (ISP), a controller… Examiner notes, Tsirkin teaches explicitly that when a VM switch is avoided, hypervisor involvement is avoided and therefore it would be obvious to one of ordinarily skilled in the art, the interrupt of Bai’s request is delivered without going through a Hypervisor for the purposes of reducing latency. See Tsirkin [0026] Using the above techniques, the guest software 112 can trigger an interrupt procedure 124 without inducing a VM exit. This may avoid transitioning from an unprivileged guest context of the virtual machine 106 to a privileged context such as the hypervisor context, which in turn can avoid the overhead typically associated with this context switching.)”.
Claim 3, 12 the combination teaches the claim, wherein Bai teaches “the method of inter-core communication according to claim 1, performing the communication between the plurality of cores using the FIQ comprises: transferring a Software Generated Interrupt (SGI) between the plurality of cores through the FIQ ([0112] According to the inter-application communication method in this embodiment of this application, the first virtual apparatus writes the first command into the first command queue based on the first request sent by the first application, and outputs the first inter-core interrupt to the core in which the second virtual apparatus is located, so that the second virtual apparatus is capable of obtaining the first inter-core interrupt and obtaining, based on the first inter-core interrupt, the first command from the first command queue, thereby implementing communication between the first virtual apparatus and the second virtual apparatus. The first command is written based on the first request from the first application, and includes the identifier of the second application on the second virtual apparatus, so that the second virtual apparatus is capable of running the second application based on the identifier that is of the second application and that is in the first command, thereby implementing communication between the application of the first virtual apparatus and the application of the second virtual apparatus. One of the first virtual apparatus and the second virtual apparatus is the virtual machine, and the other is the physical machine. Therefore, communication between the physical machine and the virtual machine is completed by directly outputting an inter-core interrupt to a core in which an object that needs to be communicated with is located, so that a virtual interrupt controller (FIQ) can be avoided to be used, thereby avoiding virtual machine entry/exit, implementing fast communication between a service of the virtual machine and a service of the physical machine, and improving communication efficiency of the electronic device.)”.
Claim/s 2, 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bai, Tsirkin in view of Yu (Pub. No. US 2023/0024628) in further view of Dai (Pub. No. US 2022/0334847).
Claim 2, 11, the combination may not explicitly teach the limitation.
Yu teaches “the method of inter-core communication according to claim 1, wherein the client is running at an exception level 1, and the Hypervisor … are running at an exception level 2 ([Fig. 3A] exception level)”.
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to apply the teachings of Yu with the teachings of Bai, Tsirkin in order to provide a system that teaches exception levels. The motivation for applying Yu teaching with Bai, Tsirkin teaching is to provide a system that allows for situational awareness. Bai, Tsirkin, Yu are analogous art directed towards interrupt processing. Together Bai, Tsirkin, Yu teaches every limitation of the claimed invention. Since the teachings were analogous art known at the filing time of invention, one of ordinary skill could have applied the teachings of Yu with the teachings of Bai, Tsirkin by known methods and gained expected results.
However, the combination may not explicitly teach the remaining limitations.
Dai teaches “the plurality of cores are running at an exception level 2 ([0046] It should be noted here that a certain processor (for example, the boot processor and/or the secondary processor) may only be in one EL at the same time. Before the preset operating system is booted, only the boot processor is in the EL1 (operating system (OS) state), while other secondary processors are in the EL2 (Hypervisor state))”.
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to apply the teachings of Dai with the teachings of Bai, Tsirkin, Yu in order to provide a system that teaches exception levels. The motivation for applying Dai teaching with Bai, Tsirkin, Yu teaching is to provide a system that allows for situational awareness. Bai, Tsirkin, Yu, Dai are analogous art directed towards interrupt processing. Together Bai, Tsirkin, Yu, Dai teach every limitation of the claimed invention. Since the teachings were analogous art known at the filing time of invention, one of ordinary skill could have applied the teachings of Dai with the teachings of Bai, Tsirkin, Yu by known methods and gained expected results.
Claim/s 4, 5, 13, 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bai, Tsirkin in further view of Grandhi (Pub. No. US 2020/0409735)
Claims 4, 13, the combination may not explicitly teach the limitation.
Grandhi teaches “the method of inter-core communication according to claim 3, wherein the transferring the SGI between the plurality of cores through the FIQ comprises: setting an interrupt number SGI ID indicating the SGI into a global variable by a source core which is a communication transmitting side among the plurality of cores ([0057] FIG. 8 is a logic flow diagram 800 illustrating local APIC pass-through logic (e.g., of the interrupt controller logic 108 of the local APIC 106A) for a logical destination mode according to one implementation. In another implementation of the APIC pass-through logic, the value within the destination field 402 of the ICR 136 includes values for the interrupt controller ID in bits ); triggering, by writing to a SGI register by the source core, a Generic Interrupt Controller (GIC) to generate the FIQ to be transmitted to a target core which is a communication receiving side among the plurality of cores; and transmitting the FIQ to the target core by the GIC, to instruct the target core to acquire the SGI ID from the global variable ([0055] With continued reference to FIG. 7, the verification just mentioned may be performed with the additional steps below the dashed line. For example, the method 700 may continue with the processing logic determining the destination mode, e.g., by reading the destination mode field 418 from the ICR (730). If the destination mode is logical, the method 700 may continue with the processing logic continuing with the method 900 of FIG. 9 (735B). If the destination mode if physical, the method 700 may continue with the processing logic converting a value in the destination field 402 into values for the cluster identifier (ID) of a cluster and an interrupt controller ID within the cluster of the one or more clusters (735A). The method 700 may continue with the processing logic accessing, with use of the pointer, the data structure to retrieve a value of the bitmap of the entry corresponding to the cluster identifier (740). The method 700 may continue with the processing logic calculating a bitwise AND of the values for the interrupt controller ID and the bitmap of the entry (745). [0056] With continued reference to FIG. 7, the method 700 may continue with the processing logic determining the result of the bitwise AND operation (750). If the result is a zero value, the method 700 may continue with the processing logic discarding the values written to the ICR, and thus no IPI is sent onto the system bus (755). If the result is no-zero, the method 700 may continue with the processing logic determining that the interrupt controller ID is associated with one of the cores of the subset of the multiple cores, and thus the IPI is sent onto the system bus (750). The IPI may be sent by sending the values in the ICR as a package onto the system bus 115 directed to the destination core.)”.
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to apply the teachings of Grandhi with the teachings of Bai, Tsirkin in order to provide a system that teaches setting destination fields. The motivation for applying Grandhi teaching with Bai, Tsirkin teaching is to provide a system that allows for situational awareness. Bai, Tsirkin, Grandhi are analogous art directed towards interrupt processing. Together Bai, Tsirkin, Grandhi teaches every limitation of the claimed invention. Since the teachings were analogous art known at the filing time of invention, one of ordinary skill could have applied the teachings of Grandhi with the teachings of Bai, Tsirkin by known methods and gained expected results.
Claims 5, 14, the combination teaches the claim, wherein Bai teaches “the method of inter-core communication according to claim 3, wherein the transferring the SGI between the plurality of cores through the FIQ comprises: receiving the FIQ by a target core, the target core being a communication receiving side among the plurality of cores, wherein the target core is one of the at least one interrupt pass-through core ([0128] Based on this, the inter-application communication method in this embodiment of this application can implement inter-core interrupt receiving/sending when the virtual interrupt controller is disabled. Because the virtual interrupt controller is disabled, both an inter-core interrupt sent by the first virtual apparatus side and an inter-core interrupt sent by the second virtual apparatus side may be directly sent to an entity that is running when the inter-core interrupt is received. [0256] The processor 110 may include one or more processing units. For example, the processor 110 may include an application processor (AP), a modem processor, a graphics processing unit (GPU), an image signal processor (ISP), a controller)”.
However, the combination may not explicitly teach the remaining limitations.
Grandhi teaches “acquiring an SGI ID indicating the SGI from a global variable by the target core in response to the FIQ being received by the target core, wherein the SGI ID is set into the global variable by a source core which is a communication transmitting side; and performing a corresponding processing by the target core based on the SGI indicated by the SGI ID ([0055] The method 700 may continue with the processing logic accessing, with use of the pointer, the data structure to retrieve a value of the bitmap of the entry corresponding to the cluster identifier (740). The method 700 may continue with the processing logic calculating a bitwise AND of the values for the interrupt controller ID and the bitmap of the entry (745). [0061] The method 900 may continue with the processing logic using the updated value in the destination field with values of the ICR to send the IPI onto the system bus (950). The IPI may be sent by sending the values in the ICR as a package onto the system bus 115 directed to the destination core.)”.
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to apply the teachings of Grandhi with the teachings of Bai, Tsirkin in order to provide a system that teaches setting destination fields. The motivation for applying Grandhi teaching with Bai, Tsirkin teaching is to provide a system that allows for situational awareness. Bai, Tsirkin, Grandhi are analogous art directed towards interrupt processing. Together Bai, Tsirkin, Grandhi teaches every limitation of the claimed invention. Since the teachings were analogous art known at the filing time of invention, one of ordinary skill could have applied the teachings of Grandhi with the teachings of Bai, Tsirkin by known methods and gained expected results.
Claim/s 9, 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bai, Tsirkin in further view of Saidi (Pat. No. US 11,042,494).
Claims 9, 18, the combination may not explicitly teach the claim.
Saidi teaches “the method of inter-core communication according to claim 1, wherein the at least one interrupt pass-through core in the interrupt pass-through mode is implemented, by configuring a register of the at least one interrupt pass-through core by the Hypervisor ([Col. 5, Lines 25-55] A physical interrupt may be an interrupt which targets a physical processor core, e.g., one of the processor cores 104. For example, the physical interrupt targeted for an ARM® core may be an IRQ, an FIQ, or a system error (SError). A virtual interrupt may be an interrupt that targets a VM executing on a processor core. Corresponding virtual interrupts for the ARM® core may be virtual IRQ, virtual FIQ, and the virtual SError. In some implementations, the IC 114 may not support direct injection of the virtual interrupt into any of the guests executing within the VMs 108a-108n. In such instances, the virtual interrupt may be injected through the hypervisor 112. For example, a virtual interrupt corresponding to a physical interrupt can be enabled and made pending by the hypervisor 112. In some implementations, the IC 114 may include list registers which can be written by the hypervisor 112 in order to register a virtual interrupt as pending. Each entry in the list can correspond to either a pending or an active interrupt, and can describe a vINTID for the virtual interrupt and a virtual priority of the interrupt among other things. The list registers can be used to assert virtual interrupts to the guest OS. The guest OS may read the list registers to process the interrupt. Thus, the injection of the virtual interrupts into a running guest through the hypervisor 112 may introduce additional latency. Therefore, it may be desirable to allow direct injection of the virtual interrupt into a running guest so that the latency for the hypervisor 112 can be avoided. Some embodiments of the disclosed technologies can allow direct injection of the virtual interrupt into a running guest even though the interrupt controller is not able to support the direct injection. This is further explained with reference to FIG. 2.)”.
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to apply the teachings of Saidi with the teachings of Bai, Tsirkin in order to provide a system that teaches setting register information. The motivation for applying Saidi teaching with Bai, Tsirkin teaching is to provide a system that allows for design choice. Bai, Tsirkin, Saidi are analogous art directed towards interrupt processing. Together Bai, Tsirkin, Saidi teaches every limitation of the claimed invention. Since the teachings were analogous art known at the filing time of invention, one of ordinary skill could have applied the teachings of Saidi with the teachings of Bai, Tsirkin by known methods and gained expected results.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WYNUEL S AQUINO whose telephone number is (571)272-7478. The examiner can normally be reached 9AM-5PM EST M-F.
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/WYNUEL S AQUINO/Primary Examiner, Art Unit 2199
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