Office Action Predictor
Last updated: April 16, 2026
Application No. 18/778,167

MODULE TRAY COVER AND SEMICONDUCTOR DEVICE CASE INCLUDING THE SAME

Non-Final OA §102
Filed
Jul 19, 2024
Examiner
SPICER, JENINE MARIE
Art Unit
3736
Tech Center
3700 — Mechanical Engineering & Manufacturing
Assignee
Samsung Electronics Co., LTD.
OA Round
1 (Non-Final)
51%
Grant Probability
Moderate
1-2
OA Rounds
3y 1m
To Grant
62%
With Interview

Examiner Intelligence

Grants 51% of resolved cases
51%
Career Allow Rate
380 granted / 749 resolved
-19.3% vs TC avg
Moderate +12% lift
Without
With
+11.8%
Interview Lift
resolved cases with interview
Typical timeline
3y 1m
Avg Prosecution
54 currently pending
Career history
803
Total Applications
across all art units

Statute-Specific Performance

§101
0.2%
-39.8% vs TC avg
§103
40.1%
+0.1% vs TC avg
§102
27.2%
-12.8% vs TC avg
§112
27.1%
-12.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 749 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Priority Acknowledgment is made of applicant's claim for foreign priority based on an application filed in Republic of Korea on 8/14/2023 and 10/30/2023. It is noted, however, that applicant has not filed a certified copy of the 10-2023-0106183 and 10-2023-0146646 applications as required by 37 CFR 1.55. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1-2, 5, 11, 13 and 15-16 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ernstberger et al. US 2014/0166533 A1. With regards to claim 1, Ernstberger discloses a module tray cover 1, comprising: a cover structure configured to cover a module tray that accommodates a plurality of semiconductor devices; a card accommodation portion 17 provided on an upper surface of the cover structure and configured to accommodate a card, the card accommodation portion providing a first accommodation space and a second accommodation space, the first accommodation space extending in a first horizontal direction, the second accommodation space (with structure 6) extend in a second horizontal direction perpendicular to the first horizontal direction and partially overlapped with the first accommodation space (shown in Fig. 4); and an upper reinforcement structure 13 including a first plurality of upper reinforcement structures and a second plurality of upper reinforcement structures, the first plurality of upper reinforcement structures being spaced apart from each other along the first horizontal direction and protruding from the upper surface of the cover structure in the first accommodation space, the second plurality of upper reinforcement structures being spaced apart from each other along the second horizontal direction and protruding from the upper surface of the cover structure in the second accommodation space, wherein the first plurality of upper reinforcement structures includes first, second and third upper reinforcement ribs sequentially disposed along the first horizontal direction from a first open side portion of the first accommodation space through which the card is inserted in the first horizontal direction, each of the first, second and third upper reinforcement ribs providing an inclined portion that has an inclined surface facing the first open side portion of the first accommodation space; and wherein the second plurality of upper reinforcement structures includes fourth, fifth and sixth upper reinforcement ribs sequentially disposed along the second horizontal direction from a second open side portion of the second accommodation space through which the card is inserted in the second horizontal direction, each of the fourth, fifth and sixth upper reinforcement ribs providing an inclined portion that has an inclined surface facing the second open side portion of the second accommodation space. With regards to claim 2, Ernstberger discloses wherein the inclined surface of the first upper reinforcement rib 13 has a first angle with respect to a first upper surface of the first upper reinforcement rib, the inclined surface of the second upper reinforcement rib has a second angle with respect to a second upper surface of the second upper reinforcement rib, and the inclined surface of the third upper reinforcement rib has a third angle with respect to a third upper surface of the third upper reinforcement rib. With regards to claim 5, Ernstberger discloses the inclined surface of the fourth upper reinforcement rib 13 has a first angle with respect to a first upper surface of the first upper reinforcement rib, the inclined surface of the fifth upper reinforcement rib has a second angle with respect to a second upper surface of the fifth upper reinforcement rib, and the inclined surface of the sixth upper reinforcement rib has a third angle with respect to a third upper surface of the sixth upper reinforcement rib. With regards to claim 11, Ernstberger discloses a module tray cover, comprising: a cover structure 1 configured to cover a module tray that accommodates a plurality of semiconductor devices, the cover structure including first and second side covers 6/17 extending in a first horizontal direction and facing each other and third and fourth side covers extending in a second horizontal direction perpendicular to the first horizontal direction and facing each other, the cover structure providing an upper region adjacent to the first side cover and a lower region adjacent to the second side cover; a card accommodation portion provided on the upper region of the cover structure and configured to accommodate a card, the card accommodation portion having a first accommodation space extending in the first horizontal direction and a second accommodation space extending in the second horizontal direction; a tag accommodation portion provided on the lower region of the cover structure and configured to accommodate a data storage device that stores data of the plurality of semiconductor devices, the tag accommodation portion including first and second protection walls extending in the first horizontal direction and facing each other, the tag accommodation portion including third and fourth protection walls extending in the second horizontal direction and facing each other; and a lower reinforcement structure disposed between the first, second, third and fourth protection walls, the lower reinforcement structure including a first lower reinforcement structure parallel with the first horizontal direction and a second lower reinforcement structure parallel with the second horizontal direction, wherein the first lower reinforcement structure includes at least one lower reinforcement rib 22 between the first protection wall and the second protection wall, the at least one lower reinforcement rib extending between the third protection wall and the fourth protection wall, and wherein the second lower reinforcement structure includes multiple lower reinforcement ribs sequentially arranged in the first horizontal direction between the third protection wall and the fourth protection wall, the multiple lower reinforcement ribs extending between the first protection wall and the second protection wall. With regards to claim 13, Ernstberger discloses the cover structure 1 has a plurality of contact portions 20 that are provided on a lower surface of the cover structure and respectively contact upper surfaces of the plurality of semiconductor devices. With regards to claim 15, Ernstberger discloses an upper reinforcement structure 13 including a first plurality of upper reinforcement structures and a second plurality of upper reinforcement structures, the first plurality of upper reinforcement structures being spaced apart along the first horizontal direction and extending between a first open side of the first accommodation space 17 and a first closed side of the first accommodation space, the first open side and the first closed side opposite each other, the second plurality of upper reinforcement structures being spaced apart along the second horizontal direction and extending between a second open side of the second accommodation space and a second closed side of the second accommodation space, the second open side and the second closed side opposite each other. With regards to claim 16, Ernstberger discloses a semiconductor device case, comprising: a module tray 1a configured to accommodate a plurality of semiconductor devices, the module tray having an open upper surface; a module tray cover 1 detachably provided on the module tray, the module tray cover including a cover structure configured to cover the open upper surface; a card accommodation portion 17 provided on an upper region of the cover structure and configured to accommodate a card, the card accommodation portion having a first accommodation space extending in a first horizontal direction and a second accommodation space extending in a second horizontal direction; a first plurality of upper reinforcement structures 13 including first, second and third upper reinforcement ribs that are sequentially disposed along the first horizontal direction from a first open side portion of the first accommodation space; a second plurality of upper reinforcement structures including fourth, fifth and sixth upper reinforcement ribs that are sequentially disposed along the second horizontal direction from a second open side portion of the second accommodation space; a tag accommodation portion spaced apart from the card accommodation portion along the second horizontal direction and configured to accommodate a data storage device that stores data of the plurality of semiconductor devices, the tag accommodation portion including first and second protection walls extending in the first horizontal direction and facing each other, the tag accommodation portion including third and fourth protection walls extending in the second horizontal direction and facing each other; and a lower 22 reinforcement structure disposed between the first to fourth protection walls, the lower reinforcement structure including a lower reinforcement structure parallel with the first horizontal direction and a plurality of lower reinforcement structures parallel with the second horizontal direction. Allowable Subject Matter Claims 3-4, 6-10, 12, 14 and 17-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: The above claims are considered allowable because the closest art of record does not disclose a module tray cover having specific dimensions with regards to the reinforcement rib angles recited in the claims, a plate having a first surface and a second surface facing away from each other; first, second, third and fourth side covers surrounding side portions of the plate, a radio frequency identification tag spaced from the card accommodation portion along the second horizontal direction and configured to store data of the plurality of semiconductor devices; and a banding guide configured to inhibit separation of a band for securing a plurality of module trays and the module tray cover as the module tray cover covers an uppermost module tray among the plurality of module trays. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to JENINE SPICER whose telephone number is (313)446-4924. The examiner can normally be reached 9:00am-5:00pm, Monday-Thursday. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Orlando E. Avilés can be reached at (571) 270-5531. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JENINE SPICER/Examiner, Art Unit 3736 /ORLANDO E AVILES/Supervisory Patent Examiner, Art Unit 3736
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Prosecution Timeline

Jul 19, 2024
Application Filed
Dec 27, 2025
Non-Final Rejection — §102
Feb 06, 2026
Interview Requested
Feb 17, 2026
Applicant Interview (Telephonic)
Feb 17, 2026
Examiner Interview Summary
Mar 30, 2026
Response Filed

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
51%
Grant Probability
62%
With Interview (+11.8%)
3y 1m
Median Time to Grant
Low
PTA Risk
Based on 749 resolved cases by this examiner. Grant probability derived from career allow rate.

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