Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
The instant detailed action is in response to Applicant's submission filed on 10 June 2026.
ALLOWABLE SUBJECT MATTER
Claim 3-6,10,15-18,22-25 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
REJECTIONS BASED ON PRIOR ART
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2,7-9,11,13-14, 19-21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chary (US PG PUB No. 2008/0082752) in view of Yamamoto (US PG PUB No. 2007/0067603).
As per claim 1, Chary discloses a method by a memory system, comprising:
receiving, by the memory system (see FIG 5A: 520) comprising a non-volatile memory having a first portion that is accessible by the memory system using address translation (see FIG 4: 485 and [0031]), operating information associated with a set of operations of a system that includes the memory system (see [0031]: “hiberfile”);
[The HDD and the non-volatile cache are taken as a non-volatile memory comprising a first portion and a second portion as recited in the claims. The HDD is accessed using an LBA of the actual data block on the HDD.]
writing, by the memory system before entering a system suspension state in which the set of operations of the system are suspended, the operating information to a second portion of the non-volatile memory (see FIG 4: 490 and [0036]),
[The NV cache is accessible without using address translation of the HDD (see FIG 7A: 730 and [0036]). The NV cache is accessed without using the address translation because the NV cache does not use the address translation component of the HDD (see also Specification [0046]: “e.g., without using the addresses translation component 230”).]
exiting the system suspension state based on an indication from a host system (see FIG 6: 610 and [0033]); and
transmitting, based on exiting the system suspension state, the operating information from the second portion of the non-volatile memory to the host system (see FIG 6: 650 and [0033]).
However, Chang does not expressly disclose
second portion of the non-volatile memory that is accessible by the memory system without using address translation
In the same field of endeavor Yamamoto discloses a non-volatile memory comprising a first portion that is accessible by the memory system using address translation and second portion of the non-volatile memory that is accessible by the memory system without using address translation (see Yamamoto FIG 14: PSA, DSA and [0079])
It would have been obvious before the effective filing date of the invention to modify Chary to further use a non-volatile memory as taught by Yamamoto.
The suggestion/motivation for doing so would have been for the benefit of a faster access to the operating information.
Therefore it would have been obvious before the effective filing date of the invention to modify Chary to further use a non-volatile memory comprising a first portion that is accessible by the memory system using address translation and second portion of the non-volatile memory that is accessible by the memory system without using address translation as taught by Yamamoto for the benefit of faster access to the operating information to arrive at the invention as specified in the claims.
As per claim 2, the method of claim 1,
wherein the second portion of the non-volatile memory has a lower access latency than the first portion of the non-volatile memory, and address translation comprises mapping a logical address to a physical address (see Yamamoto FIG 14 and [0079]).
[The PSA has a lower access latency because it is immediately accessible whereas the DSA requires constructing address translation table.]
As per claim 7, the method of claim 1,
wherein the second portion of the non-volatile memory is associated with a write pattern for writing to the second portion, the method further comprising: writing the operating information to the second portion of the non-volatile memory in accordance with the write pattern (see Chary FIG 7: 730 and [0036]).
As per claim 8, the method of claim 7,
wherein the write pattern comprises a sequential write pattern in which the operating information is written to memory blocks with sequentially indexed physical addresses (see Chary [0037]).
[The data is stored sequentially in Chary.]
As per claim 9, the method of claim 1,
wherein the operating information comprises software application information, or system state information, or any combination thereof (see Chary [0031]: “hiberfile”).
As per claim 11, the method of claim 1, further comprising:
resuming one or more operations of the set of operations based on transmitting the operating information to the host system (see Chary FIG 6: 610).
As per claim 13, the method of claim 1, further comprising:
writing, to a third portion of the non-volatile memory that is accessible by the memory system without address translation, back-up operating system information for operating the system (see Yamamoto [0076]).
As per claim 14, a method by a host system, comprising:
transmitting, to a memory system comprising a non-volatile memory having a first portion that is accessible by the memory system using address translation (see FIG 4: 485), operating information associated with a set of operations of the host system (see Chary FIG 5: 540 and [0031]);
indicating, to the memory system based on determining the host system is to enter a system suspension state in which the set of operations are suspended, that the memory system is to write the operating information to a second portion, of the non-volatile memory (see FIG 5: 560 [0032]),
receiving, based on the host system exiting the system suspension state, the operating information from the memory system (see FIG 6: 610 and [0033]); and
resuming one or more operations of the set of operations based on the operating information received from the memory system (see FIG 6: 650 and [0033]).
However, Chang does not expressly disclose
second portion of the non-volatile memory that is accessible by the memory system without using address translation
In the same field of endeavor Yamamoto discloses a non-volatile memory comprising a first portion that is accessible by the memory system using address translation and second portion of the non-volatile memory that is accessible by the memory system without using address translation (see Yamamoto FIG 14: PSA, DSA and [0079])
It would have been obvious before the effective filing date of the invention to modify Chary to further use a non-volatile memory as taught by Yamamoto.
The suggestion/motivation for doing so would have been for the benefit of a faster access to the operating information.
Therefore it would have been obvious before the effective filing date of the invention to modify Chary to further use a non-volatile memory comprising a first portion that is accessible by the memory system using address translation and second portion of the non-volatile memory that is accessible by the memory system without using address translation as taught by Yamamoto for the benefit of faster access to the operating information to arrive at the invention as specified in the claims.
As per claim 19, the method of claim 14, further comprising:
signaling, to the memory system, a state for a register of the memory system based on determining to exit the system suspension state, wherein the state indicates that the operating information is to be transmitted to the host system (see FIG 6: 640 and [033]).
As per claim 20, the method of claim 14, further comprising:
transmitting, to the memory system in association with transmitting the operating information, a command that identifies the second portion of the non-volatile memory and that indicates that the operating information is to be written to the second portion of the non-volatile memory (see Chary [034]).
As per claim 21, a method by a system, comprising:
determining, by a host system, that the system including the host system and a memory system is to enter a system suspension state in which a set of operations of the system are suspended (see Chary FIG 5: 510 and [0031]), the memory system comprising a non-volatile memory having a first portion that is accessible by the memory system using address translation (see FIG 4: 485 and [0031]);
transmitting, by the host system, operating information associated with the set of operations to the memory system based on the determination (see FIG 5: 530 and [0031]);
writing, by the memory system before the system enters the system suspension state, the operating information to a second portion of the non-volatile memory (see FIG 5: 560 and [0032]); and
receiving, from the memory system, the operating information based on the system exiting the system suspension state (see FIG 6: 610 and [0033]).
However, Chang does not expressly disclose
second portion of the non-volatile memory that is accessible by the memory system without using address translation
In the same field of endeavor Yamamoto discloses a non-volatile memory comprising a first portion that is accessible by the memory system using address translation and second portion of the non-volatile memory that is accessible by the memory system without using address translation (see Yamamoto FIG 14: PSA, DSA and [0079])
It would have been obvious before the effective filing date of the invention to modify Chary to further use a non-volatile memory as taught by Yamamoto.
The suggestion/motivation for doing so would have been for the benefit of a faster access to the operating information.
Therefore it would have been obvious before the effective filing date of the invention to modify Chary to further use a non-volatile memory comprising a first portion that is accessible by the memory system using address translation and second portion of the non-volatile memory that is accessible by the memory system without using address translation as taught by Yamamoto for the benefit of faster access to the operating information to arrive at the invention as specified in the claims.
Claim 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chary (US PG PUB No. 2008/0082752) in view of Yamamoto (US PG PUB No. 2007/0067603) as applied to claim 1 above and further in view of Thiabadeau (US Pat No. 20070180210 )
As per claim 12, the method of claim 1,
However, Chary in view of Yamamoto does not expressly disclose but in the same field of endeavor Thiabadeau discloses
wherein the second portion of the non-volatile memory is secured by a password (see Thiabadeau FIG 4: 402 and [0036]).
It would have been obvious before the effective filing date of the invention to modify Chary in view of Yamamoto to further secure the second portion of the non-volatile memory with a password.
The suggestion/motivation for doing so would have been for the benefit of access protection (see Thiabadeau [0009[).
Therefore it would have been obvious before the effective filing date of the invention to modify Chary in view of Yamamoto to further secure the second portion by a password as taught by Thiabadeau for the benefit of access protection to arrive at the invention as specified in the claims.
RESPONSE TO ARGUMENTS
The restriction requirement is withdrawn in view of Applicant’s arguments.
CONCLUSION
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. 2009/0172246: A host may initialize itself faster by enabling an associated storage device to respond to host access commands under specified conditions before the storage device has completed its own initialization. Embodiments of the invention include a storage device, a controller, a method of servicing commands, and a method of using a host that sends access commands to a storage device. Access commands to a flash memory use logical addresses to reference the memory contents. A con troller translates the logical addresses to physical addresses using a mapping table that the controller constructs in Volatile memory during initialization based on data retrieved from the flash memory. An access command satisfying a predefined condition is serviced before the controller completes the construction of the mapping table (Abstract).
DIRECTION OF FUTURE CORRESPONDENCES
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KALPIT PARIKH whose telephone number is (571)270-1173. The examiner can normally be reached MON THROUGH FRI 9:30 TO 6:00.
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/KALPIT PARIKH/
Primary Examiner, Art Unit 2137
KALPIT . PARIKH
Primary Examiner
Art Unit 2137
Prosecution Insights