DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
1. ACKNOWLEDGEMENT OF REFERENCES CITED BY APPLICANT
Information Disclosure Statement
As required by M.P.E.P. ' 609 (C), the applicant's submission of the Information Disclosure Statement, dated 8/9/24, is acknowledged by the examiner and the cited references have been considered in the examination of the claims now pending. As required by M.P.E.P. ' 609 C(2), a copy of the PTOL-1449 initialed and dated by the examiner is attached to the instant office action.
2. REJECTIONS NOT BASED ON PRIOR ART
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-20 rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 12,086,458. Although the claims at issue are not identical, they are not patentably distinct from each other because claims 1-20 of the instant application would be anticipated by claims 1-20 of the US Patent. Claim 1 of the instant application, shown in the chart below as an example, illustrates how it would be anticipated by claim 1 of the US Patent. The other independent claims and dependent claims would be rejected under a similar rationale.
Instant Application
US Patent
1. A system comprising:
a memory device comprising a programming buffer and a content addressable memory (CAM) block; and
a processing device, operatively coupled with the memory device, to perform operations comprising:
reading a first portion of each data entry of a plurality of data entries in the programming buffer;
programming the first portion of each data entry to a first CAM page of the CAM block;
reading a second portion of each data entry of the plurality of data entries in the programming buffer; and
programming the second portion of each data entry to a second CAM page of the CAM block.
1. A system comprising:
a memory device comprising a programming buffer and a content addressable memory (CAM) block; and
a processing device, operatively coupled with the memory device, to perform operations comprising:
receiving a plurality of data entries to be stored at the memory device;
storing the plurality of data entries in a plurality of pages of the programming buffer, each of the plurality of pages of the programming buffer comprising a respective subset of the plurality of data entries; and
initiating a conversion operation to copy the plurality of data entries from the programming buffer to the CAM block, wherein the conversion operation comprises:
reading respective portions of each data entry in each respective subset of the plurality of data entries from the plurality of pages of the programming buffer; and
writing the respective portions to a single CAM page of the CAM block in one program operation, wherein each data entry spans a plurality of CAM pages in the CAM block. [‘writing’ and ‘programming’ are analogous]
[taught by the same ‘reading’ limitation above as it is directed to reading multiple portions]
[taught by the same ‘writing’ limitation above as it is directed to writing multiple portions across multiple CAM pages]
3. REJECTIONS BASED ON PRIOR ART
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC ' 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 6-11, and 13-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Frost (US 7856528) in view of Lee (US 20160172037).
With respect to claim 1, the Frost reference teaches a system comprising:
a memory device comprising a programming buffer and a block; (see fig. 1, where memory storage system 100 includes memory storage array 14 [which includes blocks] and I/O buffer [not shown]; and column 8, lines 4-23, where each of the Pages of Data within an exemplary Plane (e.g., PLANE0 of DIE0 of CE3) will be associated with some specific input/output circuitry that includes an Input/Output (I/O) Buffer. The I/O Buffer is a buffer that is sized to store at least one Page of data. When data is to be written into a specific Page in a Block, a Page of data is first written to the I/O Buffer for the Plane, and the Page of data is then written into the memory locations associated with the specific Page)
a processing device, operatively coupled with the memory device, (see fig. 1, controller 10; and column 5, lines 6-16, where the FLASH controller 10 receives requests via communication bus 12 to read data stored in the FLASH memory storage array 14 and/or to store data in the FLASH memory storage array 14. The FLASH controller 10 responds to these requests either by accessing the FLASH memory storage array 14 to read or write the requested data from or into the storage array 14 in accordance with the request) to perform operations comprising:
reading a first portion of each data entry of a plurality of data entries in the programming buffer; (see fig. 3a; and column 8, line 63 to column 9, line 3, where each Page Stripe includes a number of Pages of stored data (typically provided by a host device) and one Page of data used to protect the stored data. While the actual size of a Page Stripe may vary, for purposes of the following discussion an exemplary Page Stripe consisting of nine pages of stored data and one page of data protection information [i.e. a data entry from the I/O buffer, noted above, is striped across multiple pages])
programming the first portion of each data entry to a first page of the block; (see fig. 3a; and column 8, line 63 to column 9, line 3, where each Page Stripe includes a number of Pages of stored data (typically provided by a host device) and one Page of data used to protect the stored data. While the actual size of a Page Stripe may vary, for purposes of the following discussion an exemplary Page Stripe consisting of nine pages of stored data and one page of data protection information [i.e. a data entry from the I/O buffer, noted above, is striped across multiple pages])
reading a second portion of each data entry of the plurality of data entries in the programming buffer; (see fig. 3a; and column 8, line 63 to column 9, line 3, where each Page Stripe includes a number of Pages of stored data (typically provided by a host device) and one Page of data used to protect the stored data. While the actual size of a Page Stripe may vary, for purposes of the following discussion an exemplary Page Stripe consisting of nine pages of stored data and one page of data protection information [i.e. a data entry from the I/O buffer, noted above, is striped across multiple pages]) and
programming the second portion of each data entry to a second page of the block. (see fig. 3a; and column 8, line 63 to column 9, line 3, where each Page Stripe includes a number of Pages of stored data (typically provided by a host device) and one Page of data used to protect the stored data. While the actual size of a Page Stripe may vary, for purposes of the following discussion an exemplary Page Stripe consisting of nine pages of stored data and one page of data protection information [i.e. a data entry from the I/O buffer, noted above, is striped across multiple pages])
However, the Frost reference does not explicitly teach that the block is a content addressable memory (CAM) block; and programming the first and second portion of each data entry to a first CAM page and second CAM page of the CAM block. (emphasis added)
The Lee reference teaches it is conventional to have the block be a content addressable memory (CAM) block; and programming the first and second portion of each data entry to a first CAM page and second CAM page of the CAM block. (paragraph 16, where there is a NAND-CAM array with blocks; and paragraph 28, where there is a preferred concurrent and pipeline search operation of the present invention includes totally J′×J pages [of the NAND-CAM array with blocks])
It would have been obvious to a person of ordinary skill in the art before the claimed invention was effectively filed to modify the Frost reference to have the block be a content addressable memory (CAM) block; and programming the first and second portion of each data entry to a first CAM page and second CAM page of the CAM block, as taught by the Lee reference.
The suggestion/motivation for doing so would have been to provide an improved NAND-based content-addressable memory (CAM) to achieve fast search speed and low power-consumption. (paragraph 13)
Therefore it would have been obvious to combine the Frost and Lee references for the benefits shown above to obtain the invention as specified in the claim.
With respect to claim 2, the combination of the Frost and Lee references teaches the system of claim 1, wherein the CAM block comprises an array of memory cells organized into a plurality of strings, each string comprising a plurality of memory cells connected in series between a precharged match line and a page buffer, and wherein each of the plurality of memory cells is connected to one of a plurality of search lines. (Lee, paragraph 15, where each string includes N.sub.3 cells connecting in series with a plurality of LG-based search lines laid out in parallel to the string common source line (CSL) along X-direction (word line direction) of the array and N.sub.3 WLs acting as Match lines (MLs) for Y-word search scheme with Y-direction Page Buffer (Y-PB). These MLs also work as the power lines of N.sub.2 C.sub.LBLS of the N.sub.2-bit DCRs to supply Vinh with a value of LV Vdd or a HV up to 7V and Vss during concurrent and pipeline precharge, discharge, CAM search sensing, nLC program, nLC read, nLC program-verify, and nLC erase-verify operations, etc.)
With respect to claim 3, the combination of the Frost and Lee references teaches the system of claim 2, wherein each respective CAM page of the CAM block is associated with a respective one of the plurality of search lines. (Lee, paragraph 25, where for a SLC NAND-CAM array, n=1, thus single ML for 1-page comparison is required. For a MLC NAND-CAM, n=2, then 2 MLs for 2-page comparison are required. For a TLC NAND-CAM, n=3, 3 MLs are required. An XLC NAND-CAM requires 4 MLs. In a specific embodiment, the matching-word length extends in X-direction and all nLC storage forms are compatible with those NAND nLC array without using one paired BLs for storing two complementary nLC bit data)
With respect to claim 4, the combination of the Frost and Lee references teaches the system of claim 2, wherein once each portion of a given data entry is written to the CAM block, the given data entry is stored in the CAM block along one of the plurality of strings intersecting each of the plurality of search lines. (Lee, paragraph 15, where each string includes N.sub.3 cells connecting in series with a plurality of LG-based search lines laid out in parallel to the string common source line (CSL) along X-direction (word line direction) of the array and N.sub.3 WLs acting as Match lines (MLs) for Y-word search scheme with Y-direction Page Buffer (Y-PB); and paragraph 25, where for a SLC NAND-CAM array, n=1, thus single ML for 1-page comparison is required. For a MLC NAND-CAM, n=2, then 2 MLs for 2-page comparison are required. For a TLC NAND-CAM, n=3, 3 MLs are required. An XLC NAND-CAM requires 4 MLs. In a specific embodiment, the matching-word length extends in X-direction and all nLC storage forms are compatible with those NAND nLC array without using one paired BLs for storing two complementary nLC bit data)
With respect to claim 6, the combination of the Frost and Lee references teaches the system of claim 1, wherein the memory device comprises a negative and (NAND) type flash memory device. (Lee, paragraph 13)
With respect to claim 7, the combination of the Frost and Lee references teaches system of claim 1, wherein the programming buffer is not arranged using a CAM architecture. (Frost, column 8, lines 4-23, where each of the Pages of Data within an exemplary Plane (e.g., PLANE0 of DIE0 of CE3) will be associated with some specific input/output circuitry that includes an Input/Output (I/O) Buffer. The I/O Buffer is a buffer that is sized to store at least one Page of data. When data is to be written into a specific Page in a Block, a Page of data is first written to the I/O Buffer for the Plane, and the Page of data is then written into the memory locations associated with the specific Page)
Claims 8-11 and 13-14 are the method implementation of claims 1-4 and 6-7, and rejected under a similar rationale as shown in the rejections above.
Claims 15-20 are the non-transitory machine readable storage medium implementation of claims 1-4 and 6-7, and rejected under a similar rationale as shown in the rejections above.
Claims 5 and 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Frost (US 7856528) in view of Lee (US 20160172037) as shown in the rejections above, and in further view of Kim (US 20190377495).
With respect to claim 5, the combination of the Frost and Lee references does not explicitly teach wherein the processing device is to perform operations further comprising: determining that the programming buffer is full of data entries; and responsive to determining that the programming buffer is full of data entries, initiating a conversion operation to copy the plurality of data entries from the programming buffer to the CAM block.
The Kim reference teaches it is conventional to have wherein the processing device is to perform operations further comprising: determining that the programming buffer is full of data entries; and responsive to determining that the programming buffer is full of data entries, initiating a conversion operation to copy the plurality of data entries from the programming buffer to the CAM block. (paragraph 54, where the destination SSD 220 may move the data to the NAND block 222 when the data buffer 221 is full. The data buffer 221 may be full of the data copied from the source SSD 210. The destination SSD 220 may write the data in the NAND block 222, and report a result or state of the writing to the host [where the NAND block/memory can be a CAM as noted above by the Lee reference])
It would have been obvious to a person of ordinary skill in the art before the claimed invention was effectively filed to modify the combination of the Frost and Lee references to have wherein the processing device is to perform operations further comprising: determining that the programming buffer is full of data entries; and responsive to determining that the programming buffer is full of data entries, initiating a conversion operation to copy the plurality of data entries from the programming buffer to the CAM block, as taught by the Kim reference.
The suggestion/motivation for doing so would have been to have reporting of a result or state of the writing to the host. (Kim, paragraph 54)
Therefore it would have been obvious to combine the Frost, Lee, and Kim references for the benefits shown above to obtain the invention as specified in the claim.
Claim 12 is the method implementation of claim 5, and rejected under a similar rationale as shown in the rejections above.
4. RELEVANT ART CITED BY THE EXAMINER
The following prior art made of record and not relied upon is cited to establish the level of skill in the applicant's art and those arts considered reasonably pertinent to applicant's disclosure. See MPEP 707.05(c).
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. These references include:
Moyer (US 20220319597), which teaches a memory system includes a memory device comprising a content addressable memory (CAM) block comprising a plurality of key tables each storing a respective plurality of stored search keys. The memory system further includes a processing device that receives, from a requestor, an input search key and an indication of one of the plurality of key tables and identifies a match between the input search key and one of the plurality of stored search keys in the one of the plurality of key tables. The one of the plurality of stored search keys has an associated offset value indicating a location in a sorted string table (SSTable) corresponding to the one of the plurality of key tables. The processing device further reads the offset value from the one of the plurality of key tables and returns, to the requestor, the offset value read from the one of the plurality of key tables. The requestor can retrieve, from the location in the SSTable, data representing a value associated with the input search key; and
Betz (US 20220375522), which teaches a memory system includes a memory device comprising a value data block a content addressable memory (CAM) block storing a plurality of stored search keys. The memory system further includes a processing device that receives an input search key, identifies, from the plurality of stored search keys in a CAM block of a memory device, multiple redundant copies of a stored search key that match the input search key, and determines a plurality of locations in a value data block, the plurality of locations corresponding to the multiple redundant copies, wherein one of the plurality of locations comprises a first timestamp and data representing a value associated with the input search key, and wherein a remainder of the plurality of locations comprises one or more additional timestamps. The processing device further determines whether the first timestamp matches the one or more additional timestamps, and responsive to the first timestamp matching the one or more additional timestamps, retries from the one of the plurality of locations, the data representing the value associated with the input search key.
5. CLOSING COMMENTS
Conclusion
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/PRASITH THAMMAVONG/
Primary Examiner, Art Unit 2137