Prosecution Insights
Last updated: August 17, 2026
Application No. 18/778,408

SPIKE SUPPRESSION DEVICE FOR SUPPRESSING CURRENT-SPIKE IN SWITCHED CAPACITOR CIRCUIT

Final Rejection §102
Filed
Jul 19, 2024
Priority
Dec 07, 2023 — TW 112147648
Examiner
PEREZ, BRYAN REYNALDO
Art Unit
2838
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Industrial Technology Research Institute
OA Round
2 (Final)
84%
Grant Probability
Favorable
3-4
OA Rounds
2m
Est. Remaining
98%
With Interview

Examiner Intelligence

Grants 84% — above average
84%
Career Allowance Rate
620 granted / 738 resolved
+16.0% vs TC avg
Moderate +14% lift
Without
With
+13.8%
Interview Lift
resolved cases with interview
Typical timeline
2y 3m
Avg Prosecution
29 currently pending
Career history
757
Total Applications
across all art units

Statute-Specific Performance

§101
0.4%
-39.6% vs TC avg
§103
55.7%
+15.7% vs TC avg
§102
33.1%
-6.9% vs TC avg
§112
8.5%
-31.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 738 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . This final office action is responsive to Applicants' response filed on 06/12/26. Claims 1-13 are presented for examination and are pending for the reasons indicated herein below. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. Response to Arguments Applicant's arguments filed 06/12/26 have been fully considered but they are not persuasive. Applicant argues: The inductor (L1) and diode (214) are respectively disclosed in separate and distinct embodiments of Mao's specification. Applicant submits that, combining separate embodiments within a single cited reference to account for the limitations of claim 1 (i.e., switch unit, coupled to the inductive reactance element) is an improper basis for anticipation. Applicant provides detailed arguments as follows: BIRCH (I) Mao's inductor (Li) is disclosed in an embodiment referring to FIG. 3 and paragraph [0031]. This embodiment discloses basic function of buck DC-DC converter, where inductor L1 is a basic output element (i.e., "output inductor Li" as stated in the sixth line of [0031] of Mao) and does not provide protection for buck DC-DC converter. On the other hand, Mao's diode (214) is disclosed in another distinct embodiment referring to FIG. 2 and paragraph [0027]. This embodiment discloses protection function for buck DC-DC converter, where diode (214) is a current limiting element (i.e., "comprising the diode 214 may prevent an electric current from flowing into power converter" as stated in lines [0027] of Mao), which is not the basic function of buck DC-DC converter. Mao's inductor (Li) is disclosed in an embodiment of the basic function of buck DC-DC converter, and Mao's diode (214) is disclosed in another distinct embodiment of the protection function for protecting buck DC-DC converter. Mao's inductor (Li) and diode (214) are disclosed in distinct and separate embodiments within a single cited reference. Examiner respectively disagrees: Citation is appropriate, using Mao’s [¶16] FIGS. 4 illustrates a schematic diagram of a three-terminal buck dc-dc converter and a protection device in accordance with an embodiment. Examiner is relaying only on the structure of 202 coupled to 302. This makes one embodiment to be use as a reference. Applicant argues: Even attempting to combine Mao's inductor L1 with the diode (214), it is impossible to achieve the circuit configuration of spike suppression device (100) of claim 1. Referring to last five lines of [0034] of Mao, it reveals that the protection device (202) of FIG. 2 can be used to replace the protection device (204) of FIG. 4 to improve performance. However, if the protection device (202) of FIG. 2 of Mao replaces the protection device (204) of FIG. 4, the diode (214) is not directly coupled to the inductor L1, and cannot achieve the feature of the suppression device (100) of claim 1 that "a switch unit, coupled to the inductive reactance element". Examiner respectively disagrees: Applicant is not claiming any direct connection to any components recited in the claim. Applicant argues: (III) For the switched capacitor configuration of claimed invention, inductors and diodes are NOT built-in, which does not originally include an output inductor and freewheeling diode; its energy conversion is mainly achieved through the charging and discharging mechanism of the capacitor. The claimed invention employs additional introduction of an inductor and diode for freewheeling path at the SC output. In contrast, for the synchronous buck converter of Mao, inductors and diodes are essential and built-in, which employs "inductor-based" step-down architecture, and the inductor and the body diode of the synchronous switch are essential components for circuit operation, used for energy transfer and freewheeling. Accordingly, Mao's synchronous buck converter configuration fails to disclose the additional inductor and diode in the switched capacitor configuration of claim 1. Examiner respectively disagrees: Rejection is appropriate, because based on applicant’s specifications and drawings, item 1000 (switched capacitor circuit) is shown to be the whole structure of figure 1 and does not exclude the inductor. Also claim 1 recites “…switched capacitor circuit comprises an output capacitor and at least one input capacitor, and the spike suppression device…”, the “and” infers the switched capacitor circuit includes the spike suppression device. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. Claims 1-10 rejected under 35 U.S.C. 102(a)(1) as being anticipated by Mao et al. (US 20200007037 A1) Regarding claim 1. Mao teaches a spike suppression device [fig 2, 202 w/ fig 4], for suppressing a spike current [inrush current, ¶24] in a switched capacitor circuit [302], wherein the switched capacitor circuit comprises an output capacitor and at least one input capacitor [C1 and C2], and the spike suppression device comprising: an inductive reactance element [L1], disposed between the output capacitor and the at least one input capacitor; and a switch unit [diode of 202], coupled to the inductive reactance element; wherein the inductive reactance element is configured to generate an induced voltage [voltage at L1] in response to the spike current, the induced voltage [flyback voltage of L1 discharging to C2] is opposite to the spike current [i.e. positive to negative], and the switch unit is configured to form a discharge path [202 i.e. protect against reverse polarity diode forms a path] of the inductive reactance element. Regarding claim 2. Mao teaches the spike suppression device according to claim 1, wherein the inductive reactance element is an inductor [L1]. Regarding claim 3. Mao teaches the spike suppression device according to claim 1, wherein the inductive reactance element is a wire between the output capacitor and the at least one input capacitor [L1 is a wire]. Regarding claim 4. Mao teaches the spike suppression device according to claim 1, wherein the switch unit is a diode [diode of 202], and a cathode of the diode is coupled to a first end of the inductive reactance element, and a second end of the inductive reactance element is coupled to the output capacitor. Regarding claim 5. Mao teaches the spike suppression device according to claim 1, wherein when the switched capacitor circuit operates in a charge mode [sw1 when ON], the at least one input capacitor and the output capacitor are equivalently coupled in series and receive a charge current [sw1 when ON, capacitors are understood to be equivalently in coupled in series], wherein when the spike current flows through the inductive reactance element, the induced voltage of the inductive reactance element is opposite to the spike current [¶24]. Regarding claim 6. Mao teaches the spike suppression device according to claim 1, wherein when the switched capacitor circuit operates in a discharge mode, the at least one input capacitor and the output capacitor are equivalently coupled in parallel [when sw2 is ON Vm couples capacitors in parallel] and output a discharge current [inrush current through 204], wherein when the spike current flows through the inductive reactance element, the induced voltage of the inductive reactance element is opposite to the spike current [¶24-25]. Regarding claim 7. Mao teaches the spike suppression device according to claim 1, wherein the switched capacitor circuit further comprises a plurality of switch elements [mosfets of sw1-sw2], and a first switch element [see sw1] of the switch elements is disposed between the at least one input capacitor and the inductive reactance element. Regarding claim 8. Mao teaches the spike suppression device according to claim 7, wherein when the switched capacitor circuit operates in a charge mode, the first switch element is turned ON to transmit a charge current, and the charge current flows through the inductive reactance element, and the switch unit of the spike suppression device is turned OFF [normal operation of a buck converter]. Regarding claim 9. Mao teaches the spike suppression device according to claim 8, wherein the switched capacitor circuit is coupled to a voltage source [vin] to receive the charge current, and the at least one input capacitor comprising: a first input capacitor [c1], coupled to the inductive reactance element through the first switch element; and a second input capacitor [c2], disposed between the voltage source and the first input capacitor; wherein in the charge mode, at least the first switch element is turned ON to allow the charge current to flow through the first input capacitor [i.e. upper terminal of c1], the inductive reactance element and the second input capacitor [i.e. upper terminal of c2], and the charge current does not flow through the switch unit of the spike suppression device [when sw1 is ON sw2 is OFF and thus current flows to the inductor]. Regarding claim 10. Mao teaches the spike suppression device according to claim 7, wherein when the switched capacitor circuit operates in a discharge mode, the first switch element is turned OFF, and the switch unit of the spike suppression device is turned OFF [paragraph 26 implies that switches in 202 are only used during startup phase, thus, during the discharge mode, happening after startup phase, 202 is off]. Allowable Subject Matter Claims 11-13 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, and if the claim objections stated above were overcome. Examiner Note The examiner cites particular columns and lines numbers in the references as applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner. Conclusion THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Bryan Perez whose telephone number is (571)272-8837. The examiner can normally be reached on Mon.-Fri. (7:30 – 5:00). If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Crystal Hammond, can be reached on (571) 270-1682. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://portal.uspto.gov/external/portal. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). /BRYAN R PEREZ/Examiner, Art Unit 2838
Read full office action

Prosecution Timeline

Jul 19, 2024
Application Filed
Mar 12, 2026
Non-Final Rejection mailed — §102
Jun 12, 2026
Response Filed
Jul 30, 2026
Final Rejection mailed — §102 (current)

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Prosecution Projections

3-4
Expected OA Rounds
84%
Grant Probability
98%
With Interview (+13.8%)
2y 3m (~2m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 738 resolved cases by this examiner. Grant probability derived from career allowance rate.

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