Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Non-Statutory Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
The independent claim 1 from U.S. Application 18/778,475 is compared with independent claim 1 of U.S. Patent No. 12,066,893which is shown below.
U.S. Application 18/778,475
U.S. Patent No. 12,066,893
a memory cell array including a plurality of volatile memory cells coupled to a plurality of word-lines and a plurality of bit-lines
a memory cell array including a plurality of volatile memory cells coupled to a plurality of word-lines and a plurality of bit-lines
a link error correction code (ECC) engine configured to: receive a first codeword received from a memory controller, wherein the first codeword includes main data and a first parity data
a link error correction code (ECC) engine configured to: receive a first codeword received from a memory controller, wherein the first codeword includes main data and a first parity data
and perform a first ECC decoding on the first codeword to generate the main data from the first codeword
and perform a first ECC decoding on the first codeword to generate the main data from the first codeword
a link error correction code (ECC) engine configured to: receive a first codeword received from a memory controller, wherein the first codeword includes main data and a first parity data
and perform a first ECC decoding on the first codeword to generate the main data from the first codeword
and an on-die ECC engine configured to: receive the main data from the link ECC engine
and generate a second codeword including the main data and the second parity data
perform a first ECC encoding on the main data received from the link ECC engine to generate a second parity data;
and generate a second codeword including the main data and the second parity data
and generate a second codeword including the main data and the second parity data
wherein the on-die ECC engine, in response to a result of the first ECC decoding indicating that the first codeword includes a first type of uncorrectable errors
wherein the on-die ECC engine, in response to a result of the first ECC decoding indicating that the first codeword includes a first type of uncorrectable errors
generates a third codeword by applying a first type of error pattern to the second codeword, the first type of error pattern being associated with the first type of uncorrectable errors
generates a third codeword by changing at least one of bits of the second codeword based on a first type of error pattern associated with the first type of uncorrectable errors
and provides the third codeword to a first target page of the memory cell array
and provides the third codeword to a first target page of the memory cell array
and wherein the first type of uncorrectable errors occurs during a data transmission between the memory controller and the semiconductor memory device
wherein the first type of uncorrectable errors occurs during a data transmission between the memory controller and the semiconductor memory device.
Claim 1 of U.S. Application 18/778,475 is rejected on the ground of nonstatutory obviousness-type double patenting as being unpatentable over claim 1 of U.S. Patent No. 12,066,893. Although, the conflicting claims are not identical, they are not patentably distinct from each other because claim 1 of U.S. Application 18/778,475 discloses all of the elements of the independent claim 1 of U.S. Patent No. 12,066,893, except explicitly stating and an on-die ECC engine configured to: receive the main data from the link ECC engine and perform a first ECC encoding on the main data received from the link ECC engine to generate a second parity data. However, these limitations are obvious or can be configured, as claim 1 of U.S. Application 18/778,475 already states a link error correction code (ECC) engine configured to: receive a first codeword received from a memory controller, wherein the first codeword includes main data and a first parity data; and perform a first ECC decoding on the first codeword to generate the main data from the first codeword; and generate a second codeword including the main data and the second parity data. Thus, the limitations are obvious variations of one another and can be done. Thus, it would have been obvious at a time prior to the effective filing date of Applicant’s claimed invention to have modified the teachings of claim 1 of U.S. Application 18/778,475 to include and an on-die ECC engine configured to: receive the main data from the link ECC engine and perform a first ECC encoding on the main data received from the link ECC engine to generate a second parity data is for improved performance.
Dependent claims 2-13, 15-16 and 18-20 of U.S. Application 18/778,475 are also rejected on the ground of nonstatutory obviousness-type double patenting over claims 1-11 and 18-20 of U.S. Patent No. 12,066,893 for having obvious variations.
Independent claim 14 and 17 of U.S. Application 18/778,475 is also rejected on the ground of nonstatutory obviousness-type double patenting over claim 18 of U.S Patent No. 12,066,893. The same or similar reasoning is given as provided above for claim 1.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Enam Ahmed whose telephone number is 571-270-1729. The examiner can normally be reached on Mon-Fri from 8:30 A.M. to 5:30 P.M.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Albert Decady, can be reached on 571-272-3819.
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EA
11/28/25
/ALBERT DECADY/Supervisory Patent Examiner, Art Unit 2112