DETAILED ACTION
Status of the Application
The present application is being examined under the pre-AIA first to invent provisions.
Status of the Claims
This action is in response to the applicant’s filing on July 19, 2024. Claims 21 – 38 are pending and examined below.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 20 – 30, 35 and 36 are rejected under 35 U.S.C. 103 as being unpatentable over cited U.S. Patent No. 6,445,189 B1 to Pakonen et al. (herein after "Pakonen et al. patent") in view of cited U.S. Patent Application Publication No. 2003/0227290 A1 to Parker (herein after "Parker publication"), cited U.S. Patent Application Publication No. 2005/0268264 A1 to Nagai (herein after "Nagai publication") and cited U.S. Patent No. 6,192,317 B1 to Yazici et al. (herein after “Yazici et al. patent").
Note: Text written in bold typeface is claim language from the instant application.
Texts written in normal typeface are comments made by the Examiner and/or passages from the prior art reference(s).
As to claim 20,
the Pakonen et al. patent discloses a method comprising:
measuring a current in a conductor when inducing arcing in the conductor (see Abstract);
converting the proportional voltage to a digitized voltage at the sample frequency (see Col. 4, lns 27 – 29, where "a high-frequency voltage . . . occurring in an electric network is preferably continuously digitised during several network cycles");
determining at least one noise signal according to the determined waveform of the cycle of the primary load current and the digitized current (see Col. 6, lns 53 – 54, where "Narrow-band interference peaks are easy to identify in an adjusted amplitude spectrum"); and
generating an output indicative of the positive arc detection based on the comparing when the time window is set based on values of the digitized voltage indicative of the arc (see Col. 13, lns 13 – 14, where "maximum peak value of partial discharge pulses in each phase window"; see also Col. 15, lns 52 – 55, where “Measurement data is collected during several (even hundreds or thousands) network cycles so as to be able to make statistical analyses on the behaviour of partial discharge pulses”).
The Pakonen et al. patent, however, fails to specifically disclose
converting a current from a load to a proportional voltage;
converting the current to a digitized current at a sample frequency;
determining a waveform of a cycle of a primary load current based on the digitized current;
setting by a comparator circuit a time window within a cycle of the digitized voltage by setting a start time and a stop time of a time interval based on voltage amplitude at the start time and the stop time being within a predetermined value of the peak voltage of the waveform of the cycle of the digitized voltage;
determining a model probability density at a voltage magnitude;
storing data indicative of the model probability density at the voltage magnitude in a non-transitory computer-readable medium as a reference for a positive are detection at the voltage magnitude;
determining a probability density of the at least one noise signal according to the time window set by the comparator circuit; and
comparing the probability density of the at least one noise signal with the model probability density stored on the non-transitory computer readable medium.
The Parker publication who discloses “[a] method and apparatus for detecting electrical arcs in an electrical system” discloses that “[the] sampling circuit should provide a signal which is indicative of a dynamic, time varying load characteristic of the power system: current, voltage, or impedance.” (See Abstract and ¶33.)
The Parker publication also discloses “a current signal is obtained by sampling the current flowing in the power supply circuit” and “[the] sampled signal from 25 is typically buffered by buffer 502, then converted into digital form by an Analog to Digital Converter (ADC) 504”. (See ¶36 and ¶61.)
Such disclosures suggests converting a current from a load to a proportional voltage; converting the current to a digitized current at a sample frequency; and determining a waveform of a cycle of a primary load current based on the digitized current.
Based on a reasonable expectation of success, it would have been obvious to one having ordinary skill in the art before the time the invention was filed to modify the Pakonen et al. patent to convert a current from a load to a proportional voltage, convert the current to a digitized current at a sample frequency, and determine a waveform of a cycle of a primary load current based on the digitized current, as suggested by the Parker publication, in order to track the electrical behavior of a system to avoid a dangerous condition.
The modified Pakonen et al. patent discloses the invention substantially as claimed, expect for
setting by a comparator circuit a time window within a cycle of the digitized voltage by setting a start time and a stop time of a time interval based on voltage amplitude at the start time and the stop time being within a predetermined value of the peak voltage of the waveform of the cycle of the digitized voltage;
determining a probability density of the at least one noise signal according to the time window set by the comparator circuit; and
comparing the probability density of the at least one noise signal with the model probability density stored on the non-transitory computer readable medium.
The Nagai publication, however, discloses that “a crosstalk calculating method is achieved by determining a basic noise amplitude signal applied to a victim net in a basic noise generation period specified based on a voltage signal transferred on an aggressor net in a semiconductor circuit; and by adding first and second signal portions applied to the victim net in first and second transition periods to be added to a front and back of the basic noise generation period to a front and back of the basic noise amplitude signal based on the voltage signal, respectively, to produce a noise amplitude signal.” (See 15.) In particular, the Nagai publication discloses that “the processing unit may determine a start time of the basic noise generation period based on a threshold and the voltage signal with a minimum delay, and determining an end time of the basic noise generation period based on the threshold and the voltage signal with a maximum delay.” (See ¶23.)(Emphasis added.)
Such disclosure suggests setting by a comparator circuit a time window within a cycle of the digitized voltage by setting a start time and a stop time of a time interval based on voltage amplitude at the start time and the stop time being within a predetermined value of the peak voltage of the waveform of the cycle of the digitized voltage.
Based on a reasonable expectation of success, it would have been obvious to one having ordinary skill in the art before the time the invention was filed to further modify the Pakonen et al. patent to set by a comparator circuit a time window within a cycle of the digitized voltage by setting a start time and a stop time of a time interval based on voltage amplitude at the start time and the stop time being within a predetermined value of the peak voltage of the waveform of the cycle of the digitized voltage, as suggested by the Nagai publication, in order to track the electrical behavior of a system to avoid a dangerous condition.
The modified Pakonen et al. patent discloses the invention substantially as claimed, expect for
determining a probability density of the at least one noise signal according to the time window set by the comparator circuit; and
comparing the probability density of the at least one noise signal with the model probability density stored on the non-transitory computer readable medium.
Applicant discloses that the “probability density can be represented or stored, for example, in the form of a histogram, or any other form of data representation or storage. A histogram can be indicative of a current signal associated with arcing, and can include a plurality of counts.” (See ¶19 – ¶20 of applicant disclosure.) That being said, the Yazici et al. patent discloses an equivalent arrangement where “[the] normalized joint probability mass function of phase windows 28 and PD magnitudes is computed by dividing the histogram into the total unit area.” (See Col. 3, ln 66 through Col. 4, ln 1.)
The Yazici et al. patent also discloses “. . . a condition monitoring method . . . to quantify the health of the system to predict catastrophic failures, to avoid excessive damage and unexpected down times, and to allow condition-based maintenance. The condition monitoring method acquires PD measurements periodically and compares them with past PD measurement to detect statistical deviations.” (See Col. 13, lns 18 – 25.)
Such disclosures suggest determining a probability density of the at least one noise signal according to the time window set by the comparator circuit, and comparing the probability density of the at least one noise signal with the model probability density stored on the non-transitory computer readable medium.
Based on a reasonable expectation of success, it would have been obvious to one having ordinary skill in the art before the time the invention was filed to further modify the Pakonen et al. patent to determine a probability density of the at least one noise signal according to the time window set by the comparator circuit, and compare the probability density of the at least one noise signal with the model probability density stored on the non-transitory computer readable medium, as suggested by the Yazici et al. patent, in order to facilitate statistical pattern analysis and diagnostics of partial discharge measurements of high voltage insulation.
As to claim 21,
the Pakonen et al. patent, as further modified by ¶61 of the Parker patent, which states that “[the] sampled signal from 25 is typically buffered by buffer 502, then converted into digital form by an Analog to Digital Converter (ADC) 504”, is considered to disclose a current transformer reducing the voltage to an amplitude and a DC offset suitable for an analog-to-digital conversion prior to the converting of the current to the digitized current and the converting of the voltage to the digitized voltage.
As to claim 22,
the Pakonen et al. patent discloses removing high frequency noise from the voltage. (See Col. 17, lns 24 – 26.)
As to claim 23,
the Pakonen et al. patent discloses “a high-frequency voltage (or another variable from which partial discharge pulses can be distinguished) occurring in an electric network is preferably continuously digitised during several network cycles” (See Col. 4, lns 27 – 30.) Thus, the Pakonen et al. patent is considered to disclose the sample frequency equal to a multiple of the voltage cycle frequency.
As to claim 24,
the Pakonen et al. patent, as further modified by ¶57 of the Parker patent, which states in pertinent part that “[a] suitable clock synchronization circuit 220 is shown in detail in FIG. 6 . . . This circuit will be recognized as a variation on the phase-locked loop, and will provide a clock signal which tends to remain locked in phase relationship with the AC line voltage 222”, is considered to disclose a phase locked loop determining the voltage cycle frequency.
As to claim 25,
the Pakonen et al. patent discloses that “all pulses occurring within the amplitude area are checked and the pulse parameters of the pulses that have been marked as interfering pulses are removed 119 from the database” (See Col. 11, lns 47 – 50.) Thus, the Pakonen et al. patent is considered to disclose determining one of the at least one noise signal by subtracting the determined waveform of a cycle of the primary load current from one of at least one cycle of the digitized current.
As to claim 26,
the Pakonen et al. patent discloses that “the pulse parameters of the pulses that are marked as interfering pulses are removed 207 from the database. In the method, the following parameters . . . can be changed: amplitude deviation, number of examination periods and threshold value of peak search.” (See Col. 12, ln 65 through Col. 13, ln 2.) Thus, the Pakonen et al. patent is considered to disclose adjusting the determined waveform of at least a portion of a cycle of the primary load current, according to one of the at least one noise signal.
As to claim 27,
the Pakonen et al. patent discloses that “[the] characteristic parameter Q (intensity asymmetry) shows the difference between the strengths or number of negative and positive half-cycle pulses. The difference is typically biggest, if the measured discharge has occurred in a very asymmetrical electrode structure (e.g. a corona discharge in a sharp point). Q is obtained by defining a quotient of the averages calculated from the strengths or number of the negative and positive half-cycle pulses.” (See Col. 16, lns 3 – 10.)(Emphasis added.) Thus, the Pakonen et al. patent is considered to disclose an error accumulator block being configured to adjust the determined waveform of at least a portion of a cycle of the primary load current, according to one of the at least one noise signal.
As to claim 28,
the Pakonen et al. patent discloses that “[the] first cutting 106 endeavours to remove the high peaks which strongly affect the standard deviation, in which case, in the second cutting 108, the cut level level can be defined as exactly as possible above the bottom level.” (See Col. 7, lns 32 – 36.) Thus, the Pakonen et al. patent is considered to disclose adjusting the determined waveform by adding or subtracting a fraction of the one of the at least one noise signal to or from the determined waveform of a cycle of the primary load current.
As to claim 29,
the Pakonen et al. patent discloses that “[the] amplitude area (0 to 128) is divided (step 201) into smaller examination periods like in connection with asynchronous impulse interference elimination. The amplitude area is, for instance, divided into 20 partly overlapping examination periods and the width of a period is .+-.0.055x the amplitude of the largest pulse in the pulse series. The examination periods are examined 202 one at a time and only the pulses are examined, whose amplitude is within the period.” (See Col. 12, lns 15 – 24.) Thus, the Pakonen et al. patent is considered to disclose the voltage amplitude at the start of the time interval and the stop of the time interval being within an upper portion of the peak voltage of the cycle of the digitized voltage.
As to claim 30,
the Pakonen et al. patent discloses that “[the] The width of one phase window is then 1.4.degree.). average peak value of partial discharge pulses in each phase window, number of partial discharge pulses in each phase window, histogram formed of starting voltage differences of consecutive pulses (the histogram shows the number of pulse pairs formed by consecutive pulses in each starting voltage difference window), . . . histogram formed of starting voltage differences of consecutive positive half-cycle pulses (the histogram shows the number of pulse pairs formed by consecutive positive pulses in each starting voltage difference window), and histogram formed of starting voltage differences of consecutive negative half-cycle pulses (the histogram shows the number of pulse pairs formed by consecutive negative pulses in each starting voltage difference window).” (See Col. 13, lns 17 – 36.)(Emphasis added.) The Pakonen et al. patent also discloses “[the] maximum amplitude of discharge pulses which occurred during several network cycles in each phase window”. (See Col. 15, lns 66 – 67.) Thus, the Pakonen et al. patent is considered to disclose determining the probability density of the at least one noise signal by determining a histogram indicative of the at least one noise signal, wherein the histogram comprises a plurality of counts, wherein each count is indicative of a number of amplitude bits of the at least one signal within one of a plurality of amplitude intervals, and wherein the amplitude bits are within the time window of one of the at least one noise signal..
As to claim 35,
the Pakonen et al. patent discloses “Eliminating Synchronous Impulse Interference” (See Col. 11, ln 63.) Pakonen also discloses “ pulse parameters of the pulses that are marked as interfering pulses are removed 207 from the database.” (See Col. 12, lns 65 – 66.) Thus, the Pakonen et al. patent is considered to disclose determining the probability density by excluding the one of the at least one noise signal, if a normal periodic arcing noise is determined in one of the at least one noise signals.
As to claim 36,
the Pakonen et al. patent discloses “[the] reference library 600 [comprising] typical values and their range of variation of partial discharge characteristic parameters related to most common partial discharge causes occurring in a measurement object.” (See Col. 13, lns 46 – 49.) Thus, the Pakonen et al. patent is considered to disclose the at least one model probability density comprising at least one arc probability density stored in a non-transitory computer-readable media.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 20 – 38 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 – 19 of U.S. Patent No. 12,046,889. (Hereinafter “‘889 Patent”.) Although the claims at issue are not identical, they are not patentably distinct from each other. For instance, instant claims 20 – 38 are a broader recitation of claims 1 – 19, respectively.
Claims 20 – 38 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 – 19 of U.S. Patent No. 11,522,353. (Hereinafter “‘353 Patent”.) Although the claims at issue are not identical, they are not patentably distinct from each other. For instance, instant claims 20 – 38 are a broader recitation of claims 1 – 19 of the ‘353 Patent, respectively.
Claims 20 – 38 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 – 18 and 20 of U.S. Patent No. 11,07,044. (Hereinafter “‘044 Patent”.) Although the claims at issue are not identical, they are not patentably distinct from each other. For instance, instant claims 20 – 38 are a broader recitation of claims 1 – 18 and 20 of the ‘044 Patent, respectively.
Claims 20 – 38 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 – 18 and 21 of U.S. Patent No. 10,461,519. (Hereinafter “‘519 Patent”.) Although the claims at issue are not identical, they are not patentably distinct from each other. For instance, instant claims 20 – 38 are a broader recitation of claims 1 – 18 and 21 of the ‘519 Patent, respectively.
Allowable Subject Matter
Claims 31 – 34, 37 and 38 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Examiner's Note(s): The Examiner has cited particular paragraphs or columns and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested of the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner. SEE MPEP 2141.02 [R-07.2015] VI. PRIOR ART MUST BE CONSIDERED IN ITS ENTIRETY, INCLUDING DISCLOSURES THAT TEACH AWAY FROM THE CLAIMS: A prior art reference must be considered in its entirety, i.e., as a whole, including portions that would lead away from the claimed invention. W.L. Gore & Associates, Inc. v. Garlock, Inc., 721 F.2d 1540, 220 USPQ 303 (Fed. Cir. 1983), cert, denied, 469 U.S. 851 (1984). See also MPEP §2123.
In addition, disclosures in a reference must be evaluated for what they would fairly teach one of ordinary skill in the art. See In re Snow, 471 F.2d 1400, 176 USPQ 328 (CCPA 1973) and In re Boe, 355 F.2d 961, 148 USPQ 507 (CCPA 1966). Specifically, in considering the teachings of a reference, it is proper to take into account not only the specific teachings of the reference, but also the inferences that one skilled in the art would reasonably have been expected to draw from the reference. See In re Preda, 401 F.2d 825, 159 USPQ 342 (CCPA 1968) and In re Shepard, 319 F.2d 194, 138 USPQ 148 (CCPA 1963). Likewise, it is proper to take into consideration not only the teachings of the prior art, but also the level of ordinary skill in the art. See In re Luck, 476 F.2d 650, 177 USPQ 523 (CCPA 1973). Specifically, those of ordinary skill in the art are presumed to have some knowledge of the art apart from what is expressly disclosed in the references. See In re Jacoby, 309 F.2d 513, 135 USPQ 317 (CCPA 1962).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RODNEY A. BUTLER whose telephone number is (313)446-6513. The examiner can normally be reached on weekdays, Monday through Friday, between 9 a.m. and 5 p.m. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Anne M. Antonucci can be reached on weekdays, Monday through Friday, between 9 a.m. and 5 p.m. at (313) 446-6519. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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Electronic Communications
Prior to initiating the first e-mail correspondence with any examiner, Applicant is responsible for filing a written statement with the USPTO in accordance with MPEP § 502.03 II. All received e-mail messages including e-mail attachments shall be placed into this application’s record.
/RODNEY A BUTLER/Primary Examiner, Art Unit 3666
Prosecution Insights