Detailed Action
The instant application having Application No. 18/778,482 has a total of 20 claims pending in the application; there are 3 independent claims and 17 dependent claims, all of which are ready for examination by the examiner. This Office action is in response to the claims filed 3/31/26. Claims 1-20 are pending.
NOTICE OF PRE-AIA OR AIA STATUS
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
REJECTIONS NOT BASED ON PRIOR ART
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1-20 of U.S. Patent No. 12045504 Although the claims at issue are not identical, they are not patentably distinct from each other because both claimed inventions are directed to burning in a memory system via generation of a proof of space plot; where after a cursory inspection of both claimed inventions a person of ordinary skill in the art would understand the minor differences to be obvious variants, as generating a proof of space plot involves generating lookup tables.
REJECTIONS BASED ON PRIOR ART
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 4-7, 9, 12-14 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Prendergast et al. (U.S. Patent Application Publication No. 2016/0366015), herein referred to as Prendergast et al., in view of Cohen et al. (U.S. Patent Application Publication No. 2023/0115694), herein referred to as Cohen et al.
Referring to claim 1, Prendergast et al. disclose as claimed, a device, comprising: an interface configured to be connected to a memory sub-system (see fig. 2, showing an interface connected to a memory system); and at least one processor configured to burn in the memory sub-system via generation of a lookup table in the memory sub-system (see fig. 2, showing a host processor controlling the information handling system, and see para. 32, where a burn-in process involves RF parameter values programmed into a Flash lookup table).
Prendergast et al. disclose the claimed invention except for wherein the lookup table is a set of lookup tables.
However, Cohen et al. disclose wherein the lookup table is a set of lookup tables (see para.14-18, where a plot file is generated and stored, and see para. 37-41, where generating the plot file involves generating a set of tables, the set of tables including many individual proofs of space).
Prendergast et al. and Cohen et al. are analogous art because they are from the same field of endeavor of storing data in lookup tables (see Prendergast et al., para. 5, and Cohen et al., para. 14-18).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Prendergast et al. to comprise wherein the lookup table is a set of lookup tables, as taught by Cohen et al., in order to support larger systems with multiple memories and that may involves multiple lookup tables.
Claims 9 and 16 recite similar limitations and would be rejected using the same rationale as claim 1.
As to claim 4, Prendergast et al. and Cohen et al. also disclose the device of claim 1, wherein the memory sub-system includes memory cells formed on an integrated circuit die; and the set of lookup tables are stored at least in part in the memory cells (see Prendergast et al., para. 25, where the memory may be flash memory or an EEPROM, which are formed on an integrated circuit. See Prendergast et al., para. 32, where the lookup tables are stored on flash memory).
Claim 12 recites similar limitations and would be rejected using the same rationale as claim 4.
As to claim 5, Prendergast et al. and Cohen et al. also disclose the device of claim 4, wherein the interface is configured to be connected to a host interface of the memory sub-system during an operation to burn in the memory sub-system (see Prendergast et al., para. 8, where the information handling system involves a host processing device. Also see fig. 2, showing a host processing device 205, which connects to the memory subsystem via an interface).
As to claim 6, Prendergast et al. and Cohen et al. also disclose the device of claim 5, wherein the at least one processor is configured to instruct the memory sub-system to perform at least a portion of operations to generate the set of lookup tables (see Prendergast et al., para. 40, where instructions are executed on the processing device to perform the steps disclosed).
Claim 13 recites similar limitations and would be rejected using the same rationale as claim 6.
As to claim 7, Prendergast et al. and Cohen et al. also disclose the device of claim 1, wherein the set of lookup tables corresponds to a portion of a proof of space plot (see Cohen et al., para.14-18, where a plot file is generated and stored, and see para. 37-41, where generating the plot file involves generating a set of tables, the set of tables including many individual proofs of space).
Claim 14 recites similar limitations and would be rejected using the same rationale as claim 7.
Allowable Subject Matter
Claims 2-3, 8, 10-11, 15 and 17-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for allowance: Claim 2 recites the limitation of “wherein the at least one processor configured to burn in the memory sub-system via generation of a proof of space plot containing the set of lookup tables.” This limitation is taught in the specification, para. 15-20. This limitation in combination with other recited limitations of claim 1 is not taught or suggested by the prior art of record. Dependent claims 10 and 17 recite similar limitations and would also be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Dependent claims 3, 11 and 18-20 depend on claims 2, 10 and 17 and would also be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 8 recites the limitation of “wherein the memory sub-system is a first memory sub-system; and the at least one processor is further configured to burn in a second memory sub-system via storing the portion of the proof of space plot to the second memory sub-system.” This limitation is taught in the specification, para. 15-20. This limitation in combination with other recited limitations of claim 1 is not taught or suggested by the prior art of record. Dependent claim 15 recites similar limitations and would also be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.
Response to Arguments
Applicant's arguments filed 3/31/26 have been fully considered but they are not persuasive.
Applicant argues that Prendergast and Cohen fail to disclose a memory sub-system with proof of space plots pre-generated during burn-in operations in the manufacturing of the memory sub-system. However, claim 1 does not recite proof of space plots, nor does it recite using burn-in operations in the manufacturing of the memory system. Instead, it recites an interface configured to be connected to a memory sub-system and at least one processor configured to burn in the memory sub-system via generation of a lookup table in the memory sub-system.
Prendergast et al. discloses an interface configured to be connected to a memory sub-system (see Prendergast, fig. 2, showing an interface connected to a memory system); and at least one processor configured to burn in the memory sub-system via generation of a lookup table in the memory sub-system (see Prendergast, fig. 2, showing a host processor controlling the information handling system, and see para. 32, where a burn-in process involves RF parameter values programmed into a Flash lookup table). Cohen is being combined with Prendergast et al. to teach wherein the lookup table is a set of lookup tables (see Cohen, para.14-18, where a plot file is generated and stored, and see para. 37-41, where generating the plot file involves generating a set of tables, the set of tables including many individual proofs of space).
Applicant argues that Prendergast is limited to controlling radio module transmit power performance and that Cohen is limited to cooling and retrieving block rewards. It is unclear exactly what parts of claim 1 that applicant is arguing that the prior art does not teach. It appears that the applicant is arguing that Prendergast and Cohen are unrelated art and shouldn’t be combined or that they can’t teach elements such as a lookup table, burning in memory or a processor. However, Cohen and Prendergast do teach these elements as addressed above. These are basic elements of many computer systems and well known in the art and Cohen and Prendergast both teach using lookup tables, as well as storage systems. Cohen is being combined for the teaching of using a set of lookup tables instead of a lookup table. Using multiple lookup tables is well known in the art, and it would be obvious to combine that teaching of using a set of lookup tables instead of a single lookup table in order to support larger systems with multiple memories and that may involve multiple lookup tables.
CLOSING COMMENTS
Conclusion
a. STATUS OF CLAIMS IN THE APPLICATION
The following is a summary of the treatment and status of all claims in the application as recommended by M.P.E.P. 707.07(i):
a(1) CLAIMS REJECTED IN THE APPLICATION
Per the instant office action, claims 1-20 stand rejected.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
b. DIRECTION OF FUTURE CORRESPONDENCES
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALAN OTTO whose telephone number is (571)270-1626. The examiner can normally be reached M-F 8:30AM-5:00PM.
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/A.O/Examiner, Art Unit 2132
/HOSAIN T ALAM/Supervisory Patent Examiner, Art Unit 2132
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