DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-4, 11-13 and 16-19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by [Fujimoto et al (Fig. 3); 7,190,239].
Regarding claim 1, Fujimoto et al discloses an amplifier circuit comprising a first input transistor (21a) having a gate terminal (gate terminal of 21a) coupled to an input terminal (11), a second input transistor (21b) having a gate terminal (gate terminal of 21b) coupled to the input terminal (11), a first inductor (14a) coupled to a source terminal (source terminal of 21a) of the first input transistor (21a), and a second inductor (14b) coupled to a source terminal (source terminal of 21b) of the second input transistor (21b) and wherein the second inductor (14b) is magnetically coupled to the first inductor (14a).
Regarding claim 2, wherein the second inductor (14b) is magnetically coupled to the first inductor (14a) in accordance with a magnetic coupling coefficient (coefficient of Mab), and wherein the first (21a) and second (21b) input transistors exhibit a source impedance (source impedance of 21a and 21b) that is based on the magnetic coupling coefficient (coefficient of Mab).
Regarding claims 3 and 12, wherein the second inductor (14b) is magnetically coupled to the first inductor (14a) with a magnetic coupling coefficient (coefficient of Mab), and wherein the magnetic coupling coefficient (coefficient of Mab) is based on an amount of overlap between the first inductor (14a) and second inductor (14b).
Regarding claim 4, wherein the first inductor (14a) has a first footprint (footprint of 14a), and the second inductor (14b) has a second footprint (footprint of 14b) that coincides with the first footprint (footprint of 14a).
Regarding claim 11, Fujimoto et al discloses an amplifier circuit comprising a first amplifier (21a, 14a) configured to receive a RF signal (Input) and having a first source degeneration inductor (14a), and a second amplifier (21b, 14b) configured to receive the RF signal (Input) and having a second source degeneration inductor (14b) which is magnetically coupled to the first source degeneration inductor (14a) via a magnetic coupling coefficient (coefficient of Mab) and wherein the first (21a, 14a) and second (21b, 14b) amplifiers have a source impedance (source impedance of 21a and 21b) that is based on the magnetic coupling coefficient (coefficient of Mab).
Regarding claim 13, wherein the first amplifier (21a, 14a) further comprises a first input transistor (21a) having a source terminal (source terminal of 21a) directly coupled to the first source degeneration inductor (14a), and the second amplifier (21b, 14b) further comprises a second input transistor (21b) having a source terminal (source terminal of 21b) directly coupled to the second source degeneration inductor (14b).
Regarding claim 16, Fujimoto et al discloses an amplifier circuit comprising a first amplifier (21a, 14a) having a first input (gate terminal of 21a) and a first passive electrical component (14a), and a second amplifier (21b, 14b) having a second input (gate terminal of 21b) shorted to the first input (gate terminal of 21a) and having a second passive electrical component (14b) which is magnetically coupled to the first passive electrical component (14a) for cancelling differential noise associated with the first amplifier (21a, 14a) and second amplifier (21b, 14b).
Regarding claim 17, wherein the first passive electrical component (14a) comprises a first inductor, and the second passive electrical component (14b) comprises a second inductor.
Regarding claim 18, wherein the first inductor (14a) has a first footprint (footprint of 14a), and wherein the second inductor (14b) has a second footprint (footprint of 14b) which is at least partially overlaps with the first footprint (footprint of 14a).
Regarding claim 19, wherein the first amplifier (21a, 14a) further comprises a first input transistor (21a) coupled in series with the first passive electrical component (14a), and wherein the second amplifier (21b, 14b) further comprises a second input transistor (21b) coupled in series with the second passive electrical component (14b).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 5 is rejected under 35 U.S.C. 103 as being unpatentable over [Fujimoto et al (Fig. 3); 7,190,239] in view of [Rofougaran (Fig. 4); 6,882,228].
Fujimoto et al discloses all the limitations in claim 5 except for that the series capacitor coupled between the input terminal and the gate terminals of the first and second input transistors. Rofougaran discloses an amplifier circuit comprising a series capacitor (C1) coupled between the input terminal (left terminal of C1) and the gate terminals (gate terminals of the transistors TIN1_N and TIN1_P) of the first (TIN1_N) and second (TIN1_P) input transistors. It would have been obvious to one of ordinary skill in the art at the time the invention was made would have found it obvious to have employed the series capacitor at between the input terminal and the gate terminals of the first and second input transistors of Fujimoto et al (Fig. 3), such as taught by Rofougaran (Fig. 4) in order to provide the advantageous benefit of blocking the DC signals of the amplifier circuit.
Claim(s) 6-8, 14 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over [Fujimoto et al (Fig. 3); 7,190,239] in view of [Kimball (Fig. 1); 2013/0,222,064].
Regarding claim 6, Fujimoto et al discloses all the limitations in claim 6 except for that the first transformer having a first primary coil coupled to the first input transistor. Kimball discloses an amplifier circuit comprising a first transformer (X2) having a first primary coil (right coil of X2) coupled to the first input transistor (M1). It would have been obvious to one of ordinary skill in the art at the time the invention was made would have found it obvious to have employed the first transformer at the input terminal of the first input transistor of Fujimoto et al (Fig. 3), such as taught by Kimball (Fig. 1) in order to provide the advantageous benefit of improving the transmission signals of the amplifier circuit.
Regarding claim 7, Kimball further comprising a second transformer (X3) having a second primary coil (lower winding of X3) coupled to the second input transistor (M2).
Regarding claim 8, Kimball further comprising a first cascode transistor (M3) and a second cascode transistor (M4).
Regarding claims 14 and 20, Fujimoto et al discloses all the limitations in claim 14 except for that the first amplifier further comprises a first transformer coupled in series with the first input transistor, and the second amplifier further comprises a second transformer coupled in series with the second input transistor. Kimball discloses an amplifier circuit comprising a first amplifier (X2, M1) further comprises a first transformer (X2) coupled in series with the first input transistor (M1), and the second amplifier (X3, M2) further comprises a second transformer (X3) coupled in series with the second input transistor (M2). It would have been obvious to one of ordinary skill in the art at the time the invention was made would have found it obvious to have employed the first transformer at the input terminal of the first input transistor of Fujimoto et al (Fig. 3) and the second transformer coupled in series with the second input transistor of Fujimoto et al (Fig. 3), such as taught by Kimball (Fig. 1) in order to provide the advantageous benefit of improving the transmission signals of the amplifier circuit.
Claim(s) 9, 10 and 15 is rejected under 35 U.S.C. 103 as being unpatentable over [Fujimoto et al (Fig. 3); 7,190,239] in view of [Kimball (Fig. 1); 2013/0,222,064] in further view of [Dabbagh Rezaci et al (Fig. 5); 12,149,267].
Regarding claims 9 and 15, Fujimoto et al in view of Kimball discloses all the limitations in the claims except for that the first mixer having an input coupled to the first transformer, and a second mixer having an input coupled to the second transformer. Dabbagh Rezaci et al discloses an amplifier circuit comprising a first mixer (491) having an input (input of 491) coupled to the first transformer (410), and a second mixer (490) having an input (input of 490) coupled to the second transformer (460). It would have been obvious to one of ordinary skill in the art at the time the invention was made would have found it obvious to have employed the first mixer at the input terminal of the first transformer of Kimball (Fig. 1) and the second mixer at the input terminal of the second transformer of Kimball, such as taught by Dabbagh Rezaci et al (Fig. 5) in order to provide the advantageous benefit of improving the gain control signals of the amplifier circuit.
Regarding claim 10, the limitations recited in claim 10 are obvious based on the intended use of the invention.
Conclusion
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/HENRY CHOE/ Primary Examiner, Art Unit 2843
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