DETAILED ACTION
Claims 1, 2, 4-12, and 14-20 are currently pending in the application and have been examined. Claims 1, 4, 11, 14, and 20 are amended. Claims 3 and 13 are canceled.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments filed 12/02/2025, with respect to nonstatutory obviousness-type double patenting have been fully considered and are persuasive. The nonstatutory obviousness-type double patenting rejection has been withdrawn.
The Applicant stated the following: “The Office Action objected to claims 2-10 and 12-19 for being dependent on a rejected base claim, but indicated that these claims would be allowable rewritten in independent form.” Then proceeded to amend independent claims 1, 11, and 20 to include the subject matter of dependent claims 3 and 13. The Examiner would point out that even though the Office Action should these claims as objected to in forms PTO-326 and the Index of Claims, the indication of allowable subject matter was never made in the body of the Office Action. Therefore, these claims are not allowable except where otherwise indicated and are rejected as shown below.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 2, 4-8, 11, 12, and 14-20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Rooney et al. (US-20200210278), Rooney.
Claim 1:
Rooney teaches a memory device, comprising:
a memory array;
an error correction code (ECC) circuit coupled with the memory array; and circuitry coupled with the memory array and the ECC circuit, the circuitry configured to:
receive a command associated with performing an error check and scrub (ECS) operation associated with one or more rows of memory cells;
read a code word from a row of the one or more rows based at least in part on the command, the code word corresponding to one or more addresses associated with the row; and
detect one or more errors in the code word based at least in part on reading the code word from the row in that [a]t block 210, method 200 can perform error check and scrub (ECS) operations on code words that were sensed as part of the refresh operation that was begun at block 208. Method 200 can perform ECS on as many code words as possible until the refresh operation is ready to write the data back to the target row. In various implementations, this can be a set amount or variable amount of code words, depending on whether the technology is implemented to use a constant amount of clock cycles to perform a refresh and a constant amount of clock cycles to perform ECS on a code word. In either case, method 200 can use a counter to specify which code word in the row last received ECS. Each time method 200 reaches block 200 for the same target row, it can use the counter to determine from which code word to start ECS, thus providing incremental ECS across refresh operations. In some implementations, code words that have been corrected in the past can be tagged for future out-of-order (OOO) ECS. For example, method 200 can select one of the OOO tagged codeword every fifth time ECS is run for a particular target row, which can be tracked with a second counter. Additional details on performing incremental ECS during refresh operations are provided below in relation to FIG. 3. (¶ [0037], Fig. 2 and discussion therein.)
and correct the one or more errors in the code word based at least in part on detection of the one or more errors (At step 456, ECS component 422 performs ECS on code word 424, to determine whether there are any errors, and if so to correct them, ¶ [0052]).
Claims 11 and 20:
These claims recite similar limitations as claim 1 and is rejected as such.
Claims 2, 4-8, 12, 14-20:
Rooney teaches all the aspects of these claims. (Figs. 1-4 and discussion therein).
Allowable Subject Matter
Claims 9 and 10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten to include all of the limitations of these claims in the independent claims 1, 11 and 20. None of the prior art teaches “wherein the circuitry is further configured to: receive one or more refresh commands, wherein performing the ECS operation is based at least in part on reception of the one or more refresh commands.” and “wherein reception of the one or more refresh commands are in accordance with a refresh interval time (tREFI).”
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Chung et al. (US-20180322008) could also be used to rejected the current claims and teaches A semiconductor memory device comprising: a memory cell array including a plurality of memory bank arrays, wherein each memory bank array includes a plurality of memory cell rows; an error correction circuit; an error log register; and a control logic circuit configured to control the error correction circuit to perform an error correction code (ECC) decoding sequentially on some of the memory cell rows designated by at least one internally generated address for detecting at least one bit error in each of the some memory cells, in response to a first command from a memory controller in an error check and scrub (ECS) mode, wherein the control logic circuit is configured to perform an error logging operation to write error information into each row of the error log register, and wherein the error information includes a number of error occurrence count for each of the some memory cell rows, which is determined by the control logic circuit. (Claim 1). The memory controller 100 and the semiconductor memory device 200a are connected to each other through corresponding command pins 101 and 201, corresponding address pins 102 and 202, corresponding data pins 103 and 203 and corresponding separate pins 104 and 204. The command pins 101 and 201 transmit a command signal CMD through a command transmission line TL1, the address pins 102 and 202 transmit an address signal ADDR through an address transmission line TL2, and the data pins 103 and 203 exchange main data MD in a normal mode and transmit an error information signal EIS in an error check and scrub (ECS) mode through a data transmission line TL3. The separate pins 104 and 204 transmit an alert signal ALRT to the memory controller 100 in the ECS mode. When the command CMD designates the ECS mode, the control logic circuit 210 may control the error correction circuit 400 to perform an error check and correction (ECC) decoding sequentially on each read data from some pages designated by address signal ADDR to generate an error generation signal. The control logic circuit 210 may perform an error logging operation to write page error information in each row of the error log register 460 and the page error information may include at least a number of error occurrences on each of the some pages. When the CMD is a register read command RRD, the control logic circuit 210 may provide the memory controller 100 with all or part of the page error information in the error log register 460 as the error information signal EIS. (¶¶ [0054]-[0056]).
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOHN J TABONE JR whose telephone number is (571)272-3827. The examiner can normally be reached M-F 9 AM to 7 PM EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Mark Featherstone can be reached at (571) 270-3750. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/JOHN J TABONE JR/Primary Examiner, Art Unit 2111 04/04/2026