DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This final Office action is in response to the amendment filed 6/17/26. Claims 1, 9, and 17 were amended and claims 4, 5, 12, and 13 were canceled. Claims 1-3, 6-11, and 14-20 remain pending.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claims 1-3, 6-11, and 14-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over the claims of U.S. Patent No. 11,163,490. Although the claims at issue are not identical, they are not patentably distinct from each other because the differences are not material to patentability. It is obvious to remove limitations from a patented claim (such as “data transmitted from a microchip”) and to reword other limitations (such as changing “A memory chip, comprising:” to “A device, comprising: a memory chip having”).
Instant claim 3, including independent claim 1 and intervening claim 2
Patented claim 3, including independent claim 1 and intervening claim 2
1. A device, comprising: a memory chip having:
1. A memory chip, comprising:
a first memory region; (2. The device of claim 1, wherein the first memory region is predefined.)
a predefined memory region configured to store program data transmitted from a microchip;
and a circuit configurable via first data stored in the first memory region to transfer second data to a memory outside of the memory chip; wherein the first memory region includes a command queue, and a portion of the first data is configured to control the command queue.
and a programmable engine configured to facilitate access to a second memory chip to read data from the second memory chip and write data to the second memory chip
2. The memory chip of claim 1, wherein the predefined memory region comprises a portion configured as a command queue for the programmable engine, and wherein the programmable engine is configured to facilitate access to the second memory chip according to the command queue.
3. The memory chip of claim 2, wherein a part of the program data stored in the predefined memory region is configured to control the command queue.
3. The device of claim 2, wherein the circuit includes a programmable engine configured to operate
in accordance with the first data stored in the first memory region.
according to program data stored in the predefined memory region.
Claims 1-3, 6-11, and 14-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over the claims of U.S. Patent No. 12,045,503. Although the claims at issue are not identical, they are not patentably distinct from each other because the differences are not material to patentability. It is obvious to remove limitations from a patented claim (such as mention of the second memory chip and command queue) and to reword limitations (such as changing “A system, comprising: a first memory chip” to “A device, comprising: a memory chip”).
Instant claim 3, including independent claim 1 and intervening claim 2
Patented claim 3, including independent claim 1 and intervening claim 2
1. A device, comprising: a memory chip having:
1. A system, comprising: a first memory chip; and a second memory chip connected to the first memory chip; wherein the first memory chip comprises:
a first memory region; (2. The device of claim 1, wherein the first memory region is predefined.)
a predefined memory region configured to store program data; a further memory region outside of the predefined memory region;
and a circuit configurable via first data stored in the first memory region to transfer second data to a memory outside of the memory chip; wherein the first memory region includes a command queue, and a portion of the first data is configured to control the command queue.
and a programmable engine configured in the first memory chip, wherein storing the program data in the predefined memory region causes the programmable engine to perform operations,
2. The system of claim 1, wherein a part of the program data stored in the predefined memory region is configured to control the command queue.
3. The system of claim 2, comprising a portion of memory configured to store data to be moved to the second memory chip according to the command queue.
3. The device of claim 2, wherein the circuit includes a programmable engine configured to operate
in accordance with the first data stored in the first memory region.
according to the program data, to read data from the second memory chip into the further memory region and to write data from the further memory region to the second memory chip according to the program data stored in the predefined memory region;
and wherein the predefined memory region comprises a portion configured as a command queue for the programmable engine.
Claims 1-3, 6-11, and 14-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over the claims of U.S. Patent 11,416,422. Although the claims at issue are not identical, they are not patentably distinct from each other because the differences are not material to patentability. It is obvious to remove limitations from a patented claim (such as the encryption engine and following limitations) and to reword limitations (such as changing “A memory system, comprising: a string of memory chips having at least two memory chips … a microchip” to “A system, comprising: a first memory chip … a processor chip … and a second memory chip”).
Instant claim 17
Patented claim 1
17. A system, comprising: a first memory chip having first pins and second pins; a processor chip connected to the first pins; and a second memory chip connected to the second pins;
1. A memory system, comprising: a string of memory chips having at least two memory chips, wherein: a first memory chip of the string of memory chips comprising: a first set of pins configured to couple the first memory chip to a microchip via first wiring; a second set of pins configured to couple the first memory chip to a second memory chip of the string of memory chips via second wiring that is separate from the first wiring;
wherein the first memory chip further comprises: a first memory region; and a circuit configurable via first data stored in the first memory region to transfer second data to a memory outside of the memory chip; wherein the first memory region includes a command queue, and a portion of the first data is configured to control the command queue.
a data mover configured to facilitate access to the second memory chip, via the second set of pins, to read data from the second memory chip and write data to the second memory chip;
and an encryption engine configured to encrypt data to be moved to the second memory chip; the second memory chip comprising: a third set of pins configured to couple the second memory chip to the first memory chip via the second wiring; and a fourth set of pins configured to couple the second memory chip to a third memory chip of the string of memory chips via third wiring that is separate from the first wiring and the second wiring.
Claims 1-3, 6-11, and 14-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over the claims of U.S. Patent 12,086,078. Although the claims at issue are not identical, they are not patentably distinct from each other because the differences are not material to patentability. It is obvious to remove limitations from a patented claim (such as the third memory device) and to reword limitations (such as changing “An apparatus comprising: a first memory device of a string of memory devices comprising” to “A system, comprising: a first memory chip having”).
Instant claim 17
Patented claim 1
17. A system, comprising: a first memory chip having
1. An apparatus comprising: a first memory device of a string of memory devices comprising:
first pins and second pins; a processor chip connected to the first pins; and a second memory chip connected to the second pins;
a first set of pins configured to couple the first memory device to a device having a device set of pins, wherein the device comprises a memory controller or processor, and wherein the first set of pins are directly connected via wiring to the device set of pins; and a second set of pins configured to couple the first memory device to a second memory device of the string of memory devices;
wherein the first memory chip further comprises: a first memory region; and a circuit configurable via first data stored in the first memory region to transfer second data to a memory outside of the memory chip; wherein the first memory region includes a command queue, and a portion of the first data is configured to control the command queue.
and the second memory device comprising: a third set of pins configured to couple the second memory device to the first memory device;
and a fourth set of pins configured to couple the second memory device to a third memory device, wherein, to read data from or write data to the second memory device or the third memory device, the device is configured to communicate with the first memory device and not either of the second memory device or the third memory device.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this Office action should be directed to the Examiner by phone at (571) 272-4214.
Any response to this Office action should be labeled appropriately (including serial number, Art Unit 2132, and type of response) and mailed to Commissioner for Patents, P.O. Box 1450, Alexandria, VA 22313-1450; hand-carried or delivered to the Customer Service Window at the Knox Building, 501 Dulany Street, Alexandria, VA 22314; faxed to (571) 273-8300; or filed electronically using the Patent Center.
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/Kevin Verbrugge/
Kevin Verbrugge
Primary Examiner
Art Unit 2132
Prosecution Insights