DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 2/20/26 has been entered.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over the claims of U.S. Patent No. 11,163,490. Although the claims at issue are not identical, they are not patentably distinct from each other because the differences are not material to patentability. It is obvious to remove limitations from a patented claim (such as “data transmitted from a microchip”) and to reword other limitations (such as changing “A memory chip, comprising:” to “A device, comprising: a memory chip having”).
Instant claim 3, including independent claim 1 and intervening claim 2
Patented claim 1
1. A device, comprising: a memory chip having:
1. A memory chip, comprising:
a first memory region; (2. The device of claim 1, wherein the first memory region is predefined.)
a predefined memory region configured to store program data transmitted from a microchip;
and a circuit configurable via first data stored in the first memory region to transfer second data to a memory outside of the memory chip.
3. The device of claim 2, wherein the circuit includes a programmable engine configured to operate
and a programmable engine configured to facilitate access to a second memory chip to read data from the second memory chip and write data to the second memory chip
in accordance with the first data stored in the first memory region.
according to program data stored in the predefined memory region.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over the claims of U.S. Patent No. 12,045,503. Although the claims at issue are not identical, they are not patentably distinct from each other because the differences are not material to patentability. It is obvious to remove limitations from a patented claim (such as mention of the second memory chip and command queue) and to reword limitations (such as changing “A system, comprising: a first memory chip” to “A device, comprising: a memory chip”).
Instant claim 3, including independent claim 1 and intervening claim 2
Patented claim 1
1. A device, comprising: a memory chip having:
1. A system, comprising: a first memory chip; and a second memory chip connected to the first memory chip; wherein the first memory chip comprises:
a first memory region; (2. The device of claim 1, wherein the first memory region is predefined.)
a predefined memory region configured to store program data; a further memory region outside of the predefined memory region;
and a circuit configurable via first data stored in the first memory region to transfer second data to a memory outside of the memory chip.
3. The device of claim 2, wherein the circuit includes a programmable engine configured to operate
and a programmable engine configured in the first memory chip, wherein storing the program data in the predefined memory region causes the programmable engine to perform operations,
in accordance with the first data stored in the first memory region.
according to the program data, to read data from the second memory chip into the further memory region and to write data from the further memory region to the second memory chip according to the program data stored in the predefined memory region;
and wherein the predefined memory region comprises a portion configured as a command queue for the programmable engine.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over the claims of U.S. Patent 11,416,422. Although the claims at issue are not identical, they are not patentably distinct from each other because the differences are not material to patentability. It is obvious to remove limitations from a patented claim (such as the encryption engine and following limitations) and to reword limitations (such as changing “A memory system, comprising: a string of memory chips having at least two memory chips … a microchip” to “A system, comprising: a first memory chip … a processor chip … and a second memory chip”).
Instant claim 17
Patented claim 1
17. A system, comprising: a first memory chip having first pins and second pins; a processor chip connected to the first pins; and a second memory chip connected to the second pins;
1. A memory system, comprising: a string of memory chips having at least two memory chips, wherein: a first memory chip of the string of memory chips comprising: a first set of pins configured to couple the first memory chip to a microchip via first wiring; a second set of pins configured to couple the first memory chip to a second memory chip of the string of memory chips via second wiring that is separate from the first wiring;
wherein the first memory chip further comprises: a first memory region; and a circuit configurable via first data stored in the first memory region to transfer second data to a memory outside of the memory chip.
a data mover configured to facilitate access to the second memory chip, via the second set of pins, to read data from the second memory chip and write data to the second memory chip;
and an encryption engine configured to encrypt data to be moved to the second memory chip; the second memory chip comprising: a third set of pins configured to couple the second memory chip to the first memory chip via the second wiring; and a fourth set of pins configured to couple the second memory chip to a third memory chip of the string of memory chips via third wiring that is separate from the first wiring and the second wiring.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over the claims of U.S. Patent 12,086,078. Although the claims at issue are not identical, they are not patentably distinct from each other because the differences are not material to patentability. It is obvious to remove limitations from a patented claim (such as the third memory device) and to reword limitations (such as changing “An apparatus comprising: a first memory device of a string of memory devices comprising” to “A system, comprising: a first memory chip having”).
Instant claim 17
Patented claim 1
17. A system, comprising: a first memory chip having
1. An apparatus comprising: a first memory device of a string of memory devices comprising:
first pins and second pins; a processor chip connected to the first pins; and a second memory chip connected to the second pins;
a first set of pins configured to couple the first memory device to a device having a device set of pins, wherein the device comprises a memory controller or processor, and wherein the first set of pins are directly connected via wiring to the device set of pins; and a second set of pins configured to couple the first memory device to a second memory device of the string of memory devices;
wherein the first memory chip further comprises: a first memory region; and a circuit configurable via first data stored in the first memory region to transfer second data to a memory outside of the memory chip.
and the second memory device comprising: a third set of pins configured to couple the second memory device to the first memory device;
and a fourth set of pins configured to couple the second memory device to a third memory device, wherein, to read data from or write data to the second memory device or the third memory device, the device is configured to communicate with the first memory device and not either of the second memory device or the third memory device.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication 2008/0147993 to KANEKO.
Regarding claims 1 and 9, KANEKO shows the claimed device in Fig. 1 as graphic operation unit 40.
KANEKO does not explicitly teach that graphic operation unit 40 is a memory chip, however he shows it attached to bus 36 and chips are commonly attached to buses, so it would have been obvious to one skilled in the art at the time of the effective filing date to implement graphic operation unit 40 as a chip.
KANEKO does not show the claimed first memory region, however he clearly teaches that “configuration data is transferred to the graphic operation unit 40” (see paragraph 0062) so it would have been obvious to one skilled in the art at the time of the effective filing date to include a first memory region in graphic operation unit 40 to store the configuration data.
Finally, KANEKO discloses the claimed circuit configurable via the configuration data as the graphic operation unit 40 which transfers data to and from memory outside of graphic operation unit 40 (such as main memory 50 and graphic memory 10).
Regarding claims 2 and 10, KANEKO does not mention that the memory region storing the configuration data is a predefined memory region but it would have been obvious to use a predefined memory region to store the configuration data in a deterministic fashion.
Regarding claims 3, 11, and 18, KANEKO’s graphic operation unit 40 is configured to operate in accordance with the configuration data stored therein as claimed.
Regarding claims 4, 12, and 19, KANEKO discloses a command queue in execution part 26 (see 0049). It would have been obvious to one skilled in the art at the time of the effective filing date to include a command queue in graphic operation unit 40 as well to bring the commands closer to the graphic operation unit 40 and thereby improve operation speed.
Regarding claims 6, 14, and 20, KANEKO teaches at 0058 that graphic operation unit 40 executes instructions.
Regarding claims 7 and 15, KANEKO does not teach that his memory region includes registers in graphic operation unit 40. However, he shows internal register 54 just outside of graphic operation unit 40. It would have been obvious to one skilled in the art at the time of the effective filing date to use registers as part of the memory of graphic operation unit 40 since registers are one of the fastest types of memory available and graphics processing operations are frequently sensitive to operation speed.
Regarding claims 8, 16, and 17, KANEKO does not show or mention the claimed pins, however KANEKO’s device certainly includes the claimed pins as inherent components of data transfer to and from memory chips.
Allowable Subject Matter
Claims 5 and 13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant argues at page 3, last paragraph, that the scope of instant claim 1 is different than the scope of claim 1 of each of the four related patents. In response, it is noted that the question of propriety of an obvious-type double patenting rejection does not hinge on whether a particular claim from the instant application is of different scope from a particular claim of a patent, but whether that difference is obvious.
Further, it is noted that it is not required to compare claim 1 from the instant application to claim 1 of a patent. If any claim of the instant application is obvious in view of any claim of the patent, then an obvious-type double patenting rejection is proper. The claim charts provided above show a comparison between at least one claim in the instant application with at least one claim in the patents.
Lastly, obvious-type double patenting can only be overcome by filing a terminal disclaimer or by persuasively arguing non-obviousness of the differences between the claims. Merely stating the claims are different in scope is not persuasive and is therefore not sufficient to overcome the double patenting rejections.
Note
It is noted that any citations to specific pages, columns, lines, or figures in the prior art references and any interpretation of the reference should not be considered to be limiting in any way. A reference is relevant for all it contains and may be relied upon for all that it would have reasonably suggested to one having ordinary skill in the art. See MPEP § 2123.
Conclusion
Any inquiry concerning this Office action should be directed to the Examiner by phone at (571) 272-4214.
Any response to this Office action should be labeled appropriately (including serial number, Art Unit 2132, and type of response) and mailed to Commissioner for Patents, P.O. Box 1450, Alexandria, VA 22313-1450; hand-carried or delivered to the Customer Service Window at the Knox Building, 501 Dulany Street, Alexandria, VA 22314; faxed to (571) 273-8300; or filed electronically using the Patent Center.
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/Kevin Verbrugge/
Kevin Verbrugge
Primary Examiner
Art Unit 2132