DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 12, 23, 27 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-9, 11-20, 22-30 are rejected under 35 U.S.C. 103 as being unpatentable over MolavianJazi et al. (US 20220408464 A1), hereinafter MolavianJazi in view of Ma et al. (US 20210352702 A1), hereinafter Ma.
Regarding claim 1, MolavianJazi teaches,
A network entity, comprising:
one or more memories storing processor-executable code; and (Figure 2, label 230, paragraph 0051 – Memory)
one or more processors coupled with the one or more memories and individually or collectively operable to execute the code to cause the network entity to: (Figure 2, labels 220, 225, paragraph 0046 – processor. Figure 2, label 230, paragraph 0051 - Memory)
generate one or more downlink control information (DCI) components for one or more user equipment (UEs); (Figure 11, paragraphs 0287, 0288 – procedure for using and generating DCI).
MolavianJazi fails to teach,
multiplex the one or more DCI components with downlink shared data for the one or more UEs based at least in part on a quantity of the one or more DCI components exceeding a quantity threshold, an aggregated size of the one or more DCI components exceeding a payload size threshold, or both; and
output a downlink shared channel comprising the one or more DCI components multiplexed with the downlink shared data for the one or more UEs.
However, Ma teaches,
multiplex the one or more DCI components with downlink shared data for the one or more UEs based at least in part on a quantity of the one or more DCI components exceeding a quantity threshold, an aggregated size of the one or more DCI components exceeding a payload size threshold, or both; (Figures 4, 5, labels 410a, 410b, 510a-d, paragraphs 0094, 0099 – The segmenting of the DCI into multiple DCIs is dependent on the payload size of the entire DCI. Paragraph 0100, 0101 – If the DCI payload size is too large then the DCI will be split into multiple channels. As seen in figure 5, the DCI is split into two channels each of which are multiplexed with downlink information. Paragraph 0100-0102 - Compared to figure 4 where the downlink information 405-b is not multiplexed with any DCI, in figure 5 the downlink information 505-b is multiplexed with DCI due to use of multiple channels as the payload size has been exceeded above a threshold. The payload size therefore determines whether an instance of downlink shared data will be multiplexed with the DCI).
and
output a downlink shared channel comprising the one or more DCI components multiplexed with the downlink shared data for the one or more UEs. (paragraph 0103 – The output of the multiplexing as performed in figure 5, label 530a and 530b is a shared channel).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified MolivainJazi to incorporate the shared channel and multiplexing teachings of Ma. The purpose of doing so is to mitigate the use of a single channel and for payload reduction for piggybacking (paragraph 0100, Ma).
Regarding claim 2, MolavianJazi teaches,
The network entity of claim 1, wherein, to generate the one or more DCI components, the one or more processors are individually or collectively operable to execute the code to cause the network entity to:
generate the one or more DCI components with a common cyclic redundancy check. (paragraph 0269 – UE includes information about a CRC (cyclic redundancy check).
Regarding claim 3, MolavianJazi teaches,
The network entity of claim 2, wherein the one or more processors are individually or collectively further operable to execute the code to cause the network entity to:
encode the one or more DCI components with a low density parity check code based at least in part on the aggregated size of the one or more DCI components exceeding the payload size threshold. (paragraph 0282 – Use of LDPC (low density parity check) based on exceeding a payload threshold).
Regarding claim 4, MolavianJazi teaches,
The network entity of claim 2, wherein the one or more processors are individually or collectively further operable to execute the code to cause the network entity to:
encode the one or more DCI components with a polar code based at least in part on the aggregated size of the one or more DCI components being less than the payload size threshold. (paragraph 0282 – Use of polar coding based on size being less then payload threshold).
Regarding claim 5, MolavianJazi teaches,
The network entity of claim 1, wherein, to generate the one or more DCI components, the one or more processors are individually or collectively operable to execute the code to cause the network entity to:
segment an aggregation of the one or more DCI components into a plurality of DCI segments, wherein each of the plurality of DCI segments is associated with a respective cyclic redundancy check. (paragraph 0269 – Each M-DCI field can have a separate CRC field when each M-DCI is separately coded).
Regarding claim 6, MolavianJazi teaches,
The network entity of claim 5, wherein the one or more processors are individually or collectively further operable to execute the code to cause the network entity to:
encode one or more DCI segments of the plurality of DCI segments with a low density parity check code based at least in part on a respective payload size of each of the one or more DCI segments exceeding the payload size threshold. (paragraph 0282 – The plurality (M-DCIs) can be coded using a LDPC based on the exceeding of a payload threshold).
Regarding claim 7, MolavianJazi teaches,
The network entity of claim 5, wherein the one or more processors are individually or collectively further operable to execute the code to cause the network entity to:
encode one or more DCI segments of the plurality of DCI segments with a polar code based at least in part on a respective payload size of each of the one or more DCI segments being less than the payload size threshold. (paragraph 0282 – The plurality (M-DCIs) can be coded using a polar code based on it going below a payload threshold).
Regarding claim 8, MolavianJazi teaches,
The network entity of claim 5, wherein the one or more processors are individually or collectively further operable to execute the code to cause the network entity to:
encode each of the plurality of DCI segments with a low density parity check code based at least in part on a maximum payload size associated with the plurality of DCI segments exceeding the payload size threshold. (paragraph 0282 – The plurality (M-DCIs) can be coded using a LDPC based on the exceeding of a payload threshold).
Regarding claim 9, MolavianJazi teaches,
The network entity of claim 5, wherein the one or more processors are individually or collectively further operable to execute the code to cause the network entity to:
encode each of the plurality of DCI segments with a polar code based at least in part on a minimum payload size of the plurality of DCI segments being less than the payload size threshold. (paragraph 0282 – The plurality (M-DCIs) can be coded using a polar code based on it going below a payload threshold).
Regarding claim 11, MolavianJazi teaches,
The network entity of claim 1, wherein the one or more processors are individually or collectively further operable to execute the code to cause the network entity to:
receive an indication of the quantity threshold and the payload size threshold via radio resource control signaling. (paragraph 0282 – “The total payload threshold can be specified in the system operation or be provided by higher layer signaling.”)
Regarding claim 12, MolavianJazi teaches,
A user equipment (UE), comprising:
one or more memories storing processor-executable code; and (Figure 3, label 360, paragraph 0055 – Memory)
one or more processors coupled with the one or more memories and individually or collectively operable to execute the code to cause the UE to: (Figure 3, label 340, paragraph 0060 – Processor coupled to memory)
MovavianJazi fails to teach,
receive a downlink shared channel comprising one or more downlink control information (DCI) components multiplexed with downlink shared data based at least in part on a quantity of the one or more DCI components exceeding a quantity threshold, an aggregated size of the one or more DCI components exceeding a payload size threshold, or both; and
decode the one or more DCI components, the downlink shared data, or both, to obtain downlink control information, shared data, or both for the UE.
However, Ma teaches,
receive a downlink shared channel comprising one or more downlink control information (DCI) components multiplexed with downlink shared data based at least in part on a quantity of the one or more DCI components exceeding a quantity threshold, an aggregated size of the one or more DCI components exceeding a payload size threshold, or both; and (Figures 4, 5, labels 410a, 410b, 510a-d, paragraphs 0094, 0099 – The segmenting of the DCI into multiple DCIs is dependent on the payload size of the entire DCI. Paragraph 0100, 0101 – If the DCI payload size is too large then the DCI will be split into multiple channels. As seen in figure 5, the DCI is split into two channels each of which are multiplexed with downlink information. Paragraph 0100-0102 - Compared to figure 4 where the downlink information 405-b is not multiplexed with any DCI, in figure 5 the downlink information 505-b is multiplexed with DCI due to use of multiple channels as the payload size has been exceeded above a threshold. The payload size therefore determines whether an instance of downlink shared data will be multiplexed with the DCI. Figure 2, paragraph 0087 – The transmission of the shared channels from the base station to the UE.
decode the one or more DCI components, the downlink shared data, or both, to obtain downlink control information, shared data, or both for the UE. (paragraph 0087 – The UE decodes the shared channel DCI messages).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified MolivainJazi to incorporate the shared channel , decoding, and multiplexing teachings of Ma. The purpose of doing so is to mitigate the use of a single channel and for payload reduction for piggybacking (paragraph 0100, Ma).
Regarding claim 13, MolavianJazi teaches,
The UE of claim 12, wherein, to receive the one or more DCI components, the one or more processors are individually or collectively operable to execute the code to cause the UE to:
receive the one or more DCI components with a common cyclic redundancy check. (paragraph 0269 – UE includes information about a CRC (cyclic redundancy check).
Regarding claim 14, MolavianJazi teaches,
The UE of claim 13, wherein, to receive the one or more DCI components, the one or more processors are individually or collectively operable to execute the code to cause the UE to:
receive the one or more DCI components encoded with a low density parity check code, the encoding based at least in part on the aggregated size of the one or more DCI components exceeding the payload size threshold. (paragraph 0282 – Use of LDPC (low density parity check) based on exceeding a payload threshold).
Regarding claim 15, MolavianJazi teaches,
The UE of claim 13, wherein, to receive the one or more DCI components, the one or more processors are individually or collectively operable to execute the code to cause the UE to:
receive the one or more DCI components encoded with a polar code, the encoding based at least in part on the aggregated size of the one or more DCI components being less than the payload size threshold. (paragraph 0282 – The plurality (M-DCIs) can be coded using a polar code based on the size going below a payload threshold).
Regarding claim 16, MolavianJazi teaches,
The UE of claim 12, wherein, to receive the one or more DCI components, the one or more processors are individually or collectively operable to execute the code to cause the UE to:
receive the one or more DCI components via a plurality of DCI segments, wherein each of the plurality of DCI segments is associated with a respective cyclic redundancy check. (paragraph 0269 – Each M-DCI field can have a separate CRC field when each M-DCI is separately coded).
Regarding claim 17, MolavianJazi teaches,
The UE of claim 16, wherein the one or more processors are individually or collectively further operable to execute the code to cause the UE to:
receive one or more DCI segments of the plurality of DCI segments encoded with a low density parity check code, the low density parity check code based at least in part on a respective payload size of each of the one or more DCI segments exceeding the payload size threshold. (paragraph 0282 – The plurality (M-DCIs) can be coded using a LDPC based on the exceeding of a payload threshold).
Regarding claim 18, MolavianJazi teaches,
The UE of claim 16, wherein the one or more processors are individually or collectively further operable to execute the code to cause the UE to:
receive one or more DCI segments of the plurality of DCI segments encoded with a polar code, the polar code based at least in part on a respective payload size of each of the one or more DCI segments being less than the payload size threshold. (paragraph 0282 – The plurality (M-DCIs) can be coded using a polar code based on it going below a payload threshold).
Regarding claim 19, MolavianJazi teaches,
The UE of claim 16, wherein the one or more processors are individually or collectively further operable to execute the code to cause the UE to:
receive each of the plurality of DCI segments encoded with a low density parity check code, the encoding based at least in part on a maximum payload size associated with the plurality of DCI segments exceeding the payload size threshold. (paragraph 0282 – The plurality (M-DCIs) can be coded using a LDPC based on the exceeding of a payload threshold).
Regarding claim 20, MolavianJazi teaches,
The UE of claim 16, wherein the one or more processors are individually or collectively further operable to execute the code to cause the UE to:
receive each of the plurality of DCI segments encoded with a polar code, the encoding based at least in part on a minimum payload size of the plurality of DCI segments being less than the payload size threshold. (paragraph 0282 – The plurality (M-DCIs) can be coded using a polar code based on it going below a payload threshold).
Regarding claim 22, MolavianJazi teaches,
The UE of claim 16, wherein the one or more processors are individually or collectively further operable to execute the code to cause the UE to:
transmit an indication of the quantity threshold and the payload size threshold via radio resource control signaling. (paragraph 0282 – “The total payload threshold can be specified in the system operation or be provided by higher layer signaling.”)
Claim 23 is rejected as a method of claim 1.
Claim 24 is rejected as a method of claim 2.
Claim 25 is rejected as a method of claim 3.
Claim 26 is rejected as a method of claim 5.
Claim 27 is rejected as a method of claim 12.
Claim 28 is rejected as a method of claim 13.
Claim 29 is rejected as a method of claim 14.
Claim 30 is rejected as a method of claim 16.
Claims 10, 21 are rejected under 35 U.S.C. 103 as being unpatentable over MolavianJazi in view of Ma further in view of Fan et al. (US 20210352631 A1).
Regarding claim 10, MolavianJazi in view of Ma, MolavianJazi-Ma, does not teach,
The network entity of claim 5, wherein the one or more processors are individually or collectively further operable to execute the code to cause the network entity to:
zero padding one or more DCI segments of the plurality of DCI segments base at least in part on the one or more DCI segments having a different payload size than a remaining quantity of DCI segments of the plurality of DCI segments.
Fan teaches,
The network entity of claim 5, wherein the one or more processors are individually or collectively further operable to execute the code to cause the network entity to:
zero padding one or more DCI segments of the plurality of DCI segments base at least in part on the one or more DCI segments having a different payload size than a remaining quantity of DCI segments of the plurality of DCI segments. (paragraph 0069-0073 – Using zero padding based on a difference in the size of DCI segments.)
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified MolavianJazi-Ma to incorporate the zero padding teachings of Fan. The purpose of doing so is to reduce overhead and make each DCI part the same length for the UE (paragraph 0068).
Regarding claim 21, MolavianJazi-Ma does not teach:
The UE of claim 16, wherein one or more DCI segments of the plurality of DCI segments are zero padded based at least in part on the one or more DCI segments having a different payload size than a remaining quantity of DCI segments of the plurality of DCI segmenting.
Fan teaches,
The UE of claim 16, wherein one or more DCI segments of the plurality of DCI segments are zero padded based at least in part on the one or more DCI segments having a different payload size than a remaining quantity of DCI segments of the plurality of DCI segmenting. (paragraph 0069-0073 – Using zero padding based on a difference in the size of DCI segments.)
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified MolavianJazi-Ma to incorporate the zero padding teachings of Fan. The purpose of doing so is to reduce overhead and make each DCI part the same length for the UE (paragraph 0068).
Conclusion
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/RYAN CRIGLER/ Examiner, Art Unit 2472
/NICHOLAS A JENSEN/ Supervisory Patent Examiner, Art Unit 2472
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